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Message-Id: <20210326102738.14767-4-zhangqing@rock-chips.com>
Date: Fri, 26 Mar 2021 18:27:30 +0800
From: Elaine Zhang <zhangqing@...k-chips.com>
To: robh+dt@...nel.org, heiko@...ech.de
Cc: devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org,
cl@...k-chips.com, huangtao@...k-chips.com,
kever.yang@...k-chips.com, tony.xie@...k-chips.com,
finley.xiao@...k-chips.com, Elaine Zhang <zhangqing@...k-chips.com>
Subject: [PATCH v6 03/11] arm: dts: rockchip: Fix power-controller node names for rk3288
Use more generic names (as recommended in the device tree specification
or the binding documentation)
Signed-off-by: Elaine Zhang <zhangqing@...k-chips.com>
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@...labora.com>
---
arch/arm/boot/dts/rk3288.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index ea7416c31f9b..6f4d7929e351 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -769,7 +769,7 @@
* *_HDMI HDMI
* *_MIPI_* MIPI
*/
- pd_vio@...288_PD_VIO {
+ power-domain@...288_PD_VIO {
reg = <RK3288_PD_VIO>;
clocks = <&cru ACLK_IEP>,
<&cru ACLK_ISP>,
@@ -811,7 +811,7 @@
* Note: The following 3 are HEVC(H.265) clocks,
* and on the ACLK_HEVC_NIU (NOC).
*/
- pd_hevc@...288_PD_HEVC {
+ power-domain@...288_PD_HEVC {
reg = <RK3288_PD_HEVC>;
clocks = <&cru ACLK_HEVC>,
<&cru SCLK_HEVC_CABAC>,
@@ -825,7 +825,7 @@
* (video endecoder & decoder) clocks that on the
* ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
*/
- pd_video@...288_PD_VIDEO {
+ power-domain@...288_PD_VIDEO {
reg = <RK3288_PD_VIDEO>;
clocks = <&cru ACLK_VCODEC>,
<&cru HCLK_VCODEC>;
@@ -836,7 +836,7 @@
* Note: ACLK_GPU is the GPU clock,
* and on the ACLK_GPU_NIU (NOC).
*/
- pd_gpu@...288_PD_GPU {
+ power-domain@...288_PD_GPU {
reg = <RK3288_PD_GPU>;
clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu_r>,
--
2.17.1
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