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Date:   Mon, 29 Mar 2021 15:47:26 +0200
From:   Matthias Brugger <matthias.bgg@...il.com>
To:     Chunfeng Yun <chunfeng.yun@...iatek.com>,
        Vinod Koul <vkoul@...nel.org>, Rob Herring <robh+dt@...nel.org>
Cc:     Kishon Vijay Abraham I <kishon@...com>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Chun-Kuang Hu <chunkuang.hu@...nel.org>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Jie Qiu <jie.qiu@...iatek.com>, CK Hu <ck.hu@...iatek.com>,
        Cawa Cheng <cawa.cheng@...iatek.com>,
        linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org, linux-usb@...r.kernel.org
Subject: Re: [PATCH v5 11/13] arm: dts: mt7629: harmonize node names and
 compatibles



On 16/03/2021 10:22, Chunfeng Yun wrote:
> This is used to fix dtbs_check warning
> 
> Signed-off-by: Chunfeng Yun <chunfeng.yun@...iatek.com>

Applied now to v5.12-next/dts32

> ---
> v2~v5: no changes
> ---
>  arch/arm/boot/dts/mt7629.dtsi | 12 +++++++-----
>  1 file changed, 7 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/mt7629.dtsi b/arch/arm/boot/dts/mt7629.dtsi
> index 5cbb3d244c75..874043f0490d 100644
> --- a/arch/arm/boot/dts/mt7629.dtsi
> +++ b/arch/arm/boot/dts/mt7629.dtsi
> @@ -329,8 +329,9 @@
>  			status = "disabled";
>  		};
>  
> -		u3phy0: usb-phy@...c4000 {
> -			compatible = "mediatek,generic-tphy-v2";
> +		u3phy0: t-phy@...c4000 {
> +			compatible = "mediatek,mt7629-tphy",
> +				     "mediatek,generic-tphy-v2";
>  			#address-cells = <1>;
>  			#size-cells = <1>;
>  			ranges = <0 0x1a0c4000 0xe00>;
> @@ -413,14 +414,15 @@
>  			};
>  		};
>  
> -		pciephy1: pcie-phy@...4a000 {
> -			compatible = "mediatek,generic-tphy-v2";
> +		pciephy1: t-phy@...4a000 {
> +			compatible = "mediatek,mt7629-tphy",
> +				     "mediatek,generic-tphy-v2";
>  			#address-cells = <1>;
>  			#size-cells = <1>;
>  			ranges = <0 0x1a14a000 0x1000>;
>  			status = "disabled";
>  
> -			pcieport1: port1phy@0 {
> +			pcieport1: pcie-phy@0 {
>  				reg = <0 0x1000>;
>  				clocks = <&clk20m>;
>  				clock-names = "ref";
> 

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