linux-kernel - Re: [PATCH v4 22/22] x86/fpu/xstate: Introduce boot-parameters to control state component support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <87r1jy6oer.ffs@nanos.tec.linutronix.de>
Date:   Mon, 29 Mar 2021 16:10:52 +0200
From:   Thomas Gleixner <tglx@...utronix.de>
To:     Len Brown <lenb@...nel.org>
Cc:     Andy Lutomirski <luto@...nel.org>,
        "Chang S. Bae" <chang.seok.bae@...el.com>,
        Borislav Petkov <bp@...e.de>, Ingo Molnar <mingo@...nel.org>,
        X86 ML <x86@...nel.org>, "Brown\, Len" <len.brown@...el.com>,
        Dave Hansen <dave.hansen@...el.com>,
        "Liu\, Jing2" <jing2.liu@...el.com>,
        "Ravi V. Shankar" <ravi.v.shankar@...el.com>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Linux Documentation List <linux-doc@...r.kernel.org>
Subject: Re: [PATCH v4 22/22] x86/fpu/xstate: Introduce boot-parameters to control state component support

On Mon, Mar 29 2021 at 09:31, Len Brown wrote:
> On Sat, Mar 27, 2021 at 6:20 PM Thomas Gleixner <tglx@...utronix.de> wrote:
>
>> What's the actual downside of issuing TILERELEASE conditionally
>> depending on prev->AMX INIT=0? Is it slooooow or what's the real
>> problem here?
>
> TILERELEASE is fast, so there should be no down-side to execute it.
> Indeed, checking whether you need to execute it or not will probably take
> longer than executing TILERELEASE.  My point (perhaps academic)
> is that Linux should not have to know about TILERELEASE, or execute it.
>
> Re: running in the kernel with AMX INIT=0
>
> AMX INIT=0 will prevent c6 on that core.  I don't expect to see this
> in the syscall path, though if a user wanted to neglect to issue TILERELEASE,
> there is nothing forcing them to do so.
>
> It can certainly happen on the interrupt path, but on the interrupt patch
> I don't know if we can end up requesting c6 -- perhaps on a forced
> task migration?

I think I clearly described how it can end up in that situation and that
there are a gazillion ways to get there.

If I decide at 5PM to call it a day after hitting the breakpoint, then I
really would appreciate that the machine goes deep idle instead of
staying at C1(E) until 9AM when I come back.

> Re:  frequency credits in the kernel with AMX INIT=0.
>
> It works exactly the same way as AMX INIT=1.
> That is to say, the frequency credits don't key off of AMX INIT,
> they key off of the actual use of the AMX execution unit, and
> the credits free up several orders of magnitude faster
> (both for AVX-512 and AMX) on this hardware as in previous generations.
>
> As a result, if we interrupt an AMX program, and run for an extended
> period of time in the kernel without XRESTOR to clear out his AMX INIT=0 state,
> that will not have any impact on the frequency we run inside the kernel any more
> than if he had AMX INIT=1 state.

Ok. That's clearly missing in documentation, but it does not solve the C
state issue at all.

Thanks,

        tglx