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Message-ID: <20210329155843.GD5166@sirena.org.uk>
Date: Mon, 29 Mar 2021 16:58:43 +0100
From: Mark Brown <broonie@...nel.org>
To: Brad Larson <brad@...sando.io>
Cc: linux-arm-kernel@...ts.infradead.org, arnd@...db.de,
linus.walleij@...aro.org, bgolaszewski@...libre.com,
fancer.lancer@...il.com, adrian.hunter@...el.com,
ulf.hansson@...aro.org, olof@...om.net, linux-gpio@...r.kernel.org,
linux-spi@...r.kernel.org, linux-mmc@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 03/13] spi: dw: Add support for Pensando Elba SoC SPI
On Sun, Mar 28, 2021 at 06:59:28PM -0700, Brad Larson wrote:
> @@ -56,7 +56,7 @@ struct dw_spi_mscc {
> /*
> * The Designware SPI controller (referred to as master in the documentation)
> * automatically deasserts chip select when the tx fifo is empty. The chip
> - * selects then needs to be either driven as GPIOs or, for the first 4 using the
> + * selects then needs to be either driven as GPIOs or, for the first 4 using
> * the SPI boot controller registers. the final chip select is an OR gate
> * between the Designware SPI controller and the SPI boot controller.
> */
This is an unrelated fix, please send as a separate patch as covered in
submitting-patches.rst.
> @@ -237,6 +237,31 @@ static int dw_spi_canaan_k210_init(struct platform_device *pdev,
> return 0;
> }
>
> +static void dw_spi_elba_set_cs(struct spi_device *spi, bool enable)
> +{
> + struct dw_spi *dws = spi_master_get_devdata(spi->master);
> +
> + if (!enable) {
> + /*
> + * Using a GPIO-based chip-select, the DW SPI
> + * controller still needs its own CS bit selected
> + * to start the serial engine. On Elba the specific
> + * CS doesn't matter to start the serial engine,
> + * so using CS0.
> + */
Why does this comment only apply to one branch of the conditional?
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