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Message-Id: <20210331232356.2204476-3-adrien.grassein@gmail.com>
Date: Thu, 1 Apr 2021 01:23:54 +0200
From: Adrien Grassein <adrien.grassein@...il.com>
To: unlisted-recipients:; (no To-header on input)
Cc: robh+dt@...nel.org, shawnguo@...nel.org, s.hauer@...gutronix.de,
kernel@...gutronix.de, festevam@...il.com, linux-imx@....com,
catalin.marinas@....com, will@...nel.org,
bjorn.andersson@...aro.org, krzk@...nel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org,
Adrien Grassein <adrien.grassein@...il.com>
Subject: [PATCH v3 2/4] arm64: dts: imx8mq-nitrogen: add USB HOST support
Add the description for the USB host port.
This port is linked to a resettable USB HUB so handle
this reset signal with a GPIO hog.
Signed-off-by: Adrien Grassein <adrien.grassein@...il.com>
---
.../boot/dts/freescale/imx8mq-nitrogen.dts | 30 +++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts
index b46f45a82be1..04992cbba56e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts
@@ -102,6 +102,14 @@ ethphy0: ethernet-phy@4 {
};
};
+&gpio1 {
+ usb-host-reset-hog {
+ gpio-hog;
+ gpios = <14 GPIO_ACTIVE_HIGH>;
+ output-high;
+ };
+};
+
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
@@ -213,6 +221,22 @@ &usb3_phy0 {
status = "okay";
};
+&usb_dwc3_1 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+/*
+ * On this board, USB host is connected to a resettable hub.
+ * The reset signal is connected to the GPIO <&gpio1 14 GPIO_ACTIVE_LOW>.
+ * You need to activate it in the bootloader or in the userspace.
+ */
+&usb3_phy1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb3_1>;
+};
+
&usdhc1 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
assigned-clock-rates = <400000000>;
@@ -388,6 +412,12 @@ MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x16
>;
};
+ pinctrl_usb3_1: usb3-1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16
+ >;
+ };
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
--
2.25.1
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