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Message-ID: <161715705952.2260335.14485382500737180840@swboyd.mtv.corp.google.com>
Date: Tue, 30 Mar 2021 19:17:39 -0700
From: Stephen Boyd <sboyd@...nel.org>
To: Richard Zhu <hongxing.zhu@....com>, abel.vesa@....com,
ping.bai@....com, shawnguo@...nel.org
Cc: linux-imx@....com, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
Richard Zhu <hongxing.zhu@....com>
Subject: Re: [PATCH] clk: imx8mq: Correct the pcie1 sels
Quoting Richard Zhu (2021-03-15 01:17:48)
> - The sys2_pll_50m should be one of the clock sels of PCIE_AUX clock.
> Change the sys2_pll_500m to sys2_pll_50m.
> - Correct one mis-spell of the imx8mq_pcie1_ctrl_sels definition, from
> "sys2_pll_250m" to "sys2_pll_333m".
>
> Signed-off-by: Richard Zhu <hongxing.zhu@....com>
> ---
Any Fixes tag?
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