linux-kernel - Re: [PATCH 10/24] ARM: at91: sfrbu: add sfrbu registers definitions for sama7g5

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Date:   Thu, 1 Apr 2021 09:34:27 +0000
From:   <Claudiu.Beznea@...rochip.com>
To:     <alexandre.belloni@...tlin.com>
CC:     <Nicolas.Ferre@...rochip.com>, <Ludovic.Desroches@...rochip.com>,
        <robh+dt@...nel.org>, <linux@...linux.org.uk>,
        <linux-arm-kernel@...ts.infradead.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 10/24] ARM: at91: sfrbu: add sfrbu registers definitions
 for sama7g5

On 31.03.2021 18:54, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On 31/03/2021 13:58:54+0300, Claudiu Beznea wrote:
>> Add SFRBU registers definitions for SAMA7G5.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea@...rochip.com>
>> ---
>>  include/soc/at91/sama7-sfrbu.h | 34 ++++++++++++++++++++++++++++++++++
>>  1 file changed, 34 insertions(+)
>>  create mode 100644 include/soc/at91/sama7-sfrbu.h
>>
>> diff --git a/include/soc/at91/sama7-sfrbu.h b/include/soc/at91/sama7-sfrbu.h
>> new file mode 100644
>> index 000000000000..76b740810d34
>> --- /dev/null
>> +++ b/include/soc/at91/sama7-sfrbu.h
>> @@ -0,0 +1,34 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>> +/*
>> + * Microchip SAMA7 SFRBU registers offsets and bit definitions.
>> + *
>> + * Copyright (C) [2020] Microchip Technology Inc. and its subsidiaries
>> + *
>> + * Author: Claudu Beznea <claudiu.beznea@...rochip.com>
>> + */
>> +
>> +#ifndef __SAMA7_SFRBU_H__
>> +#define __SAMA7_SFRBU_H__
>> +
>> +#ifdef CONFIG_SOC_SAMA7
>> +
>> +#define AT91_SFRBU_PSWBU                     (0x00)          /* SFRBU Power Switch BU Control Register */
>> +#define              AT91_SFRBU_PSWBU_PSWKEY         (0x4BD20C << 8) /* Specific value mandatory to allow writing of other register bits */
>> +#define              AT91_SFRBU_PSWBU_STATE          (1 << 2)        /* Power switch BU state */
>> +#define              AT91_SFRBU_PSWBU_SOFTSWITCH     (1 << 1)        /* Power switch BU source selection */
>> +#define              AT91_SFRBU_PSWBU_CTRL           (1 << 0)        /* Power switch BU control */
> 
> Please use BIT
> 
>> +
>> +#define AT91_SFRBU_25LDOCR                   (0x0C)          /* SFRBU 2.5V LDO Control Register */
>> +#define              AT91_SFRBU_25LDOCR_LDOANAKEY    (0x3B6E18 << 8) /* Specific value mandatory to allow writing of other register bits. */
>> +#define              AT91_SFRBU_25LDOCR_STATE        (1 << 3)        /* LDOANA Switch On/Off Control */
>> +#define              AT91_SFRBU_25LDOCR_LP           (1 << 2)        /* LDOANA Low-Power Mode Control */
>> +#define              AT91_SFRBU_PD_VALUE_MSK         (0x3)
> 
> GENMASK
> 
>> +#define              AT91_SFRBU_25LDOCR_PD_VALUE(v)  ((v) & AT91_SFRBU_PD_VALUE_MSK) /* LDOANA Pull-down value */
> 
> this macro is not necessary, you can use FIELD_PREP with the previous
> define.
> 

This file (as well as include/soc/at91/sama7-ddr.h) is used in
arch/arm/mach-at91/pm_suspend.S who's content is executed from CPU internal
SRAM. I chose to have these defines w/o BIT(), GENMASK() and friends to not
depend on the bitops.h who's size might be changed at any time.

> 
> --
> Alexandre Belloni, co-owner and COO, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
>