linux-kernel - Re: [PATCH v2 4/5] iommu/vt-d: Use user privilege for RID2PASID translation

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Message-ID: <84f0ca29-04e0-446b-745a-73e2f9e49f3b@linux.intel.com>
Date:   Tue, 6 Apr 2021 08:58:08 +0800
From:   Lu Baolu <baolu.lu@...ux.intel.com>
To:     Joerg Roedel <joro@...tes.org>, Will Deacon <will@...nel.org>
Cc:     baolu.lu@...ux.intel.com, iommu@...ts.linux-foundation.org,
        linux-kernel@...r.kernel.org,
        Jacob Pan <jacob.jun.pan@...ux.intel.com>
Subject: Re: [PATCH v2 4/5] iommu/vt-d: Use user privilege for RID2PASID
 translation

On 3/20/21 10:54 AM, Lu Baolu wrote:
> When first-level page tables are used for IOVA translation, we use user
> privilege by setting U/S bit in the page table entry. This is to make it
> consistent with the second level translation, where the U/S enforcement
> is not available. Clear the SRE (Supervisor Request Enable) field in the
> pasid table entry of RID2PASID so that requests requesting the supervisor
> privilege are blocked and treated as DMA remapping faults.
> 
> Suggested-by: Jacob Pan <jacob.jun.pan@...ux.intel.com>
> Fixes: b802d070a52a1 ("iommu/vt-d: Use iova over first level")
> Signed-off-by: Lu Baolu <baolu.lu@...ux.intel.com>

We found some devices still require SRE to be set during internal tests.
I will drop this patch from my queue for v5.13 for now.

Best regards,
baolu

> ---
>   drivers/iommu/intel/iommu.c | 7 +++++--
>   drivers/iommu/intel/pasid.c | 3 ++-
>   2 files changed, 7 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
> index 868f195f55ff..7354f9ce47d8 100644
> --- a/drivers/iommu/intel/iommu.c
> +++ b/drivers/iommu/intel/iommu.c
> @@ -2494,9 +2494,9 @@ static int domain_setup_first_level(struct intel_iommu *iommu,
>   				    struct device *dev,
>   				    u32 pasid)
>   {
> -	int flags = PASID_FLAG_SUPERVISOR_MODE;
>   	struct dma_pte *pgd = domain->pgd;
>   	int agaw, level;
> +	int flags = 0;
>   
>   	/*
>   	 * Skip top levels of page tables for iommu which has
> @@ -2512,7 +2512,10 @@ static int domain_setup_first_level(struct intel_iommu *iommu,
>   	if (level != 4 && level != 5)
>   		return -EINVAL;
>   
> -	flags |= (level == 5) ? PASID_FLAG_FL5LP : 0;
> +	if (pasid != PASID_RID2PASID)
> +		flags |= PASID_FLAG_SUPERVISOR_MODE;
> +	if (level == 5)
> +		flags |= PASID_FLAG_FL5LP;
>   
>   	return intel_pasid_setup_first_level(iommu, dev, (pgd_t *)pgd, pasid,
>   					     domain->iommu_did[iommu->seq_id],
> diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
> index 0bf7e0a76890..dd69df5a188a 100644
> --- a/drivers/iommu/intel/pasid.c
> +++ b/drivers/iommu/intel/pasid.c
> @@ -673,7 +673,8 @@ int intel_pasid_setup_second_level(struct intel_iommu *iommu,
>   	 * Since it is a second level only translation setup, we should
>   	 * set SRE bit as well (addresses are expected to be GPAs).
>   	 */
> -	pasid_set_sre(pte);
> +	if (pasid != PASID_RID2PASID)
> +		pasid_set_sre(pte);
>   	pasid_set_present(pte);
>   	pasid_flush_caches(iommu, pte, pasid, did);
>   
>