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Date: Tue, 6 Apr 2021 17:04:45 +0800
From: Zhiqiang Hou <Zhiqiang.Hou@....com>
To: linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
lorenzo.pieralisi@....com, robh+dt@...nel.org, bhelgaas@...gle.com,
shawnguo@...nel.org, leoyang.li@....com,
gustavo.pimentel@...opsys.com
Cc: minghuan.Lian@....com, mingkai.hu@....com, roy.zang@....com,
Hou Zhiqiang <Zhiqiang.Hou@....com>
Subject: [PATCHv4 2/6] dt-bindings: pci: layerscape-pci: Add a optional property big-endian
From: Hou Zhiqiang <Zhiqiang.Hou@....com>
This property is to indicate the endianness when accessing the
PEX_LUT and PF register block, so if these registers are
implemented in big-endian, specify this property.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@....com>
Acked-by: Rob Herring <robh@...nel.org>
---
V4:
- Rebased against the latest code base
Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index 6d898dd4a8e2..d633c1fabdb4 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -40,6 +40,10 @@ Required properties:
of the data transferred from/to the IP block. This can avoid the software
cache flush/invalid actions, and improve the performance significantly.
+Optional properties:
+- big-endian: If the PEX_LUT and PF register block is in big-endian, specify
+ this property.
+
Example:
pcie@...0000 {
--
2.17.1
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