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Message-Id: <20210406090449.36352-5-Zhiqiang.Hou@nxp.com>
Date: Tue, 6 Apr 2021 17:04:47 +0800
From: Zhiqiang Hou <Zhiqiang.Hou@....com>
To: linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
lorenzo.pieralisi@....com, robh+dt@...nel.org, bhelgaas@...gle.com,
shawnguo@...nel.org, leoyang.li@....com,
gustavo.pimentel@...opsys.com
Cc: minghuan.Lian@....com, mingkai.hu@....com, roy.zang@....com,
Hou Zhiqiang <Zhiqiang.Hou@....com>
Subject: [PATCHv4 4/6] dt-bindings: pci: layerscape-pci: Update the description of SCFG property
From: Hou Zhiqiang <Zhiqiang.Hou@....com>
Update the description of the second entry of 'fsl,pcie-scfg' property,
as the LS1043A PCIe controller also has some control registers in SCFG
block, while it has 3 controllers.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@....com>
Acked-by: Rob Herring <robh@...nel.org>
---
V4:
- Rebased against the latest code base
Documentation/devicetree/bindings/pci/layerscape-pci.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index d633c1fabdb4..8231f6729385 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -34,7 +34,7 @@ Required properties:
"intr": The interrupt that is asserted for controller interrupts
- fsl,pcie-scfg: Must include two entries.
The first entry must be a link to the SCFG device node
- The second entry must be '0' or '1' based on physical PCIe controller index.
+ The second entry is the physical PCIe controller index starting from '0'.
This is used to get SCFG PEXN registers
- dma-coherent: Indicates that the hardware IP block can ensure the coherency
of the data transferred from/to the IP block. This can avoid the software
--
2.17.1
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