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Message-Id: <20210406113631.2675029-3-fparent@baylibre.com>
Date: Tue, 6 Apr 2021 13:36:30 +0200
From: Fabien Parent <fparent@...libre.com>
To: Rob Herring <robh+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>
Cc: mkorpershoek@...libre.com, Fabien Parent <fparent@...libre.com>,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: [PATCH v3 3/3] arm64: dts: mediatek: mt8167: add some DRM nodes
Add all the DRM nodes required to get DSI to work on MT8167 SoC.
Signed-off-by: Fabien Parent <fparent@...libre.com>
---
Note: This series is based on https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=v5.12-next/dts64-2
V3:
* Removed unicode character in commit summary
V2:
* No changes
arch/arm64/boot/dts/mediatek/mt8167.dtsi | 149 +++++++++++++++++++++++
1 file changed, 149 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
index 9029051624a6..17942095944e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
@@ -16,6 +16,19 @@
/ {
compatible = "mediatek,mt8167";
+ aliases {
+ aal0 = &aal;
+ ccorr0 = &ccorr;
+ color0 = &color;
+ dither0 = &dither;
+ dsi0 = &dsi;
+ ovl0 = &ovl0;
+ pwm0 = &disp_pwm;
+ rdma0 = &rdma0;
+ rdma1 = &rdma1;
+ wdma0 = &wdma;
+ };
+
soc {
topckgen: topckgen@...00000 {
compatible = "mediatek,mt8167-topckgen", "syscon";
@@ -114,6 +127,13 @@ vdecsys: syscon@...00000 {
#clock-cells = <1>;
};
+ mutex: mutex@...15000 {
+ compatible = "mediatek,mt8167-disp-mutex";
+ reg = <0 0x14015000 0 0x1000>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ };
+
pio: pinctrl@...0b000 {
compatible = "mediatek,mt8167-pinctrl";
reg = <0 0x1000b000 0 0x1000>;
@@ -126,6 +146,135 @@ pio: pinctrl@...0b000 {
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
};
+ rdma1: rdma1@...0a000 {
+ compatible = "mediatek,mt8167-disp-rdma",
+ "mediatek,mt2701-disp-rdma";
+ reg = <0 0x1400a000 0 0x1000>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA1>;
+ iommus = <&iommu M4U_PORT_DISP_RDMA1>;
+ mediatek,larb = <&larb0>;
+ };
+
+ disp_pwm: disp_pwm@...0f000 {
+ compatible = "mediatek,mt8167-disp-pwm",
+ "mediatek,mt8173-disp-pwn";
+ reg = <0 0x1100f000 0 0x1000>;
+ #pwm-cells = <2>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ clocks = <&topckgen CLK_TOP_PWM_SEL>,
+ <&topckgen CLK_TOP_PWM_MM>,
+ <&mmsys CLK_MM_DISP_PWM_26M>,
+ <&mmsys CLK_MM_DISP_PWM_MM>;
+ clock-names = "pwm_sel",
+ "pwm_mm",
+ "main",
+ "mm";
+ status = "disabled";
+ };
+
+ dsi: dsi@...12000 {
+ compatible = "mediatek,mt8167-dsi",
+ "mediatek,mt2701-dsi";
+ reg = <0 0x14012000 0 0x1000>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DSI_ENGINE>,
+ <&mmsys CLK_MM_DSI_DIGITAL>,
+ <&mipi_tx>;
+ clock-names = "engine", "digital", "hs";
+ phys = <&mipi_tx>;
+ phy-names = "dphy";
+ status = "disabled";
+ };
+
+ mipi_tx: mipi_dphy@...18000 {
+ compatible = "mediatek,mt8167-mipi-tx",
+ "mediatek,mt2701-mipi-tx";
+ reg = <0 0x14018000 0 0x90>;
+ clocks = <&topckgen CLK_TOP_MIPI_26M_DBG>;
+ clock-output-names = "mipi_tx0_pll";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ ovl0: ovl0@...07000 {
+ compatible = "mediatek,mt8167-disp-ovl",
+ "mediatek,mt8173-disp-ovl";
+ reg = <0 0x14007000 0 0x1000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ iommus = <&iommu M4U_PORT_DISP_OVL0>;
+ mediatek,larb = <&larb0>;
+ };
+
+ rdma0: rdma0@...09000 {
+ compatible = "mediatek,mt8167-disp-rdma",
+ "mediatek,mt2701-disp-rdma";
+ reg = <0 0x14009000 0 0x1000>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+ iommus = <&iommu M4U_PORT_DISP_RDMA0>;
+ mediatek,larb = <&larb0>;
+ };
+
+ color: color@...0c000 {
+ compatible = "mediatek,mt8167-disp-color",
+ "mediatek,mt8173-disp-color";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_COLOR>;
+ };
+
+ ccorr: ccorr@...0d000 {
+ compatible = "mediatek,mt8167-disp-ccorr",
+ "mediatek,mt8183-disp-ccorr";
+ reg = <0 0x1400d000 0 0x1000>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_CCORR>;
+ };
+
+ aal: aal@...0e000 {
+ compatible = "mediatek,mt8167-disp-aal";
+ reg = <0 0x1400e000 0 0x1000>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_AAL>;
+ };
+
+ gamma: gamma@...0f000 {
+ compatible = "mediatek,mt8167-disp-gamma",
+ "mediatek,mt8173-disp-gamma";
+ reg = <0 0x1400f000 0 0x1000>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_GAMMA>;
+ };
+
+ dither: dither@...10000 {
+ compatible = "mediatek,mt8167-disp-dither";
+ reg = <0 0x14010000 0 0x1000>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_DITHER>;
+ };
+
+ wdma: wdma0@...0b000 {
+ compatible = "mediatek,mt8167-disp-wdma";
+ reg = <0 0x1400b000 0 0x1000>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_WDMA>;
+ iommus = <&iommu M4U_PORT_DISP_WDMA0>;
+ mediatek,larb = <&larb0>;
+ };
+
mmsys: mmsys@...00000 {
compatible = "mediatek,mt8167-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
--
2.31.0
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