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Message-ID: <CAE2upjQFnAkKVWWZmOt4u=rTEb5QjP7j+-ZgfOXkMA663THDDw@mail.gmail.com>
Date: Wed, 7 Apr 2021 11:49:13 -0400
From: Rajneesh Bhardwaj <irenic.rajneesh@...il.com>
To: "David E. Box" <david.e.box@...ux.intel.com>
Cc: hdegoede@...hat.com, mgross@...ux.intel.com,
gayatri.kammela@...el.com, platform-driver-x86@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 9/9] platform/x86: intel_pmc_core: Add support for Alder
Lake PCH-P
Acked-by: Rajenesh Bhardwaj <irenic.rajneesh@...il.com>
On Wed, Mar 31, 2021 at 11:06 PM David E. Box
<david.e.box@...ux.intel.com> wrote:
>
> Alder PCH-P is based on Tiger Lake PCH.
>
> Signed-off-by: David E. Box <david.e.box@...ux.intel.com>
> ---
> drivers/platform/x86/intel_pmc_core.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
> index 9168062c927e..88d582df829f 100644
> --- a/drivers/platform/x86/intel_pmc_core.c
> +++ b/drivers/platform/x86/intel_pmc_core.c
> @@ -1440,6 +1440,7 @@ static const struct x86_cpu_id intel_pmc_core_ids[] = {
> X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, &tgl_reg_map),
> X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, &icl_reg_map),
> X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE, &tgl_reg_map),
> + X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, &tgl_reg_map),
> {}
> };
>
> --
> 2.25.1
>
--
Thanks,
Rajneesh
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