lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Wed, 7 Apr 2021 03:02:21 +0000
From:   "Voon, Weifeng" <weifeng.voon@...el.com>
To:     Andrew Lunn <andrew@...n.ch>
CC:     "Sit, Michael Wei Hong" <michael.wei.hong.sit@...el.com>,
        "peppe.cavallaro@...com" <peppe.cavallaro@...com>,
        "alexandre.torgue@...com" <alexandre.torgue@...com>,
        "joabreu@...opsys.com" <joabreu@...opsys.com>,
        "davem@...emloft.net" <davem@...emloft.net>,
        "kuba@...nel.org" <kuba@...nel.org>,
        "mcoquelin.stm32@...il.com" <mcoquelin.stm32@...il.com>,
        "linux@...linux.org.uk" <linux@...linux.org.uk>,
        "Ong, Boon Leong" <boon.leong.ong@...el.com>,
        "qiangqing.zhang@....com" <qiangqing.zhang@....com>,
        "Wong, Vee Khee" <vee.khee.wong@...el.com>,
        "fugang.duan@....com" <fugang.duan@....com>,
        "Chuah, Kim Tatt" <kim.tatt.chuah@...el.com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "linux-stm32@...md-mailman.stormreply.com" 
        <linux-stm32@...md-mailman.stormreply.com>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "hkallweit1@...il.com" <hkallweit1@...il.com>
Subject: RE: [PATCH net-next v2 0/2] Enable 2.5Gbps speed for stmmac

> > The limitation is not on the MAC, PCS or the PHY. For Intel mgbe, the
> > overclocking of 2.5 times clock rate to support 2.5G is only able to
> > be configured in the BIOS during boot time. Kernel driver has no
> > access to modify the clock rate for 1Gbps/2.5G mode. The way to
> > determined the current 1G/2.5G mode is by reading a dedicated adhoc
> register through mdio bus.
> > In short, after the system boot up, it is either in 1G mode or 2.5G
> > mode which not able to be changed on the fly.
> 
> Right. It would of been a lot easier if this was in the commit message
> from the beginning. Please ensure the next version does say this.
> 
> > Since the stmmac MAC can pair with any PCS and PHY, I still prefer
> > that we tie this platform specific limitation with the of MAC. As
> > stmmac does handle platform specific config/limitation.
> 
> So yes, this needs to be somewhere in the intel specific stmmac code,
> with a nice comment explaining what is going on.
> 
> What PHY are you using? The Aquantia/Marvell multi-gige phy can do rate
> adaptation. So you could fix the MAC-PHY link to 2500BaseX, and let the
> PHY internally handle the different line speeds.
> 
Intel mgbe is flexible to pair with any PHY. Only Aquantia/Marvell
multi-gige PHY can do rate adaption right? Hence, we still need to take 
care of others PHYs.

Thanks for all the comments, will include them in v3. 

Weifeng

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ