linux-kernel - [PATCH v1 0/7] imx-gpcv2 improvements

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Message-Id: <20210407212122.626137-1-adrien.grassein@gmail.com>
Date:   Wed,  7 Apr 2021 23:21:15 +0200
From:   Adrien Grassein <adrien.grassein@...il.com>
To:     unlisted-recipients:; (no To-header on input)
Cc:     robh+dt@...nel.org, shawnguo@...nel.org, s.hauer@...gutronix.de,
        kernel@...gutronix.de, festevam@...il.com, linux-imx@....com,
        l.stach@...gutronix.de, Anson.Huang@....com, krzk@...nel.org,
        peng.fan@....com, aisheng.dong@....com, qiangqing.zhang@....com,
        alice.guo@....com, aford173@...il.com, agx@...xcpu.org,
        andrew.smirnov@...il.com, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        Adrien Grassein <adrien.grassein@...il.com>
Subject: [PATCH v1 0/7] imx-gpcv2 improvements

Hi,

This patch set aims is to add the support of the i.MX8 MM power domains
on the mainline kernel.

To achieve this, I do several patches
  - Check errors when reading or writing registers (concerns i.MX8M base
    implementation);
  - Fix power up/down sequence. Handshake was not checked and it was
    not called at the appropriate time (concerns i.MX8M base
implementaions);
  - Allow domains without power sequence control like the HSIOMIX of the
    i.MX8MM.
  - Add some i.MX8MM domains (HSIO and OTGS);
  - Introduce quirks. For example, i.MX8MM OTG domains should not be
    powered off (seen n the source code of th i.MX ATF). Quirks are
easily upgrable for other cases.
  - Finally I defined power domains into the imx8mm.dtb file.

I know that this kind of patch is rejected by NXP ut the other way
(callin ATF directly) was also rejected.

I also know that NXP is concerned abou adding hundred lines of codes for
each new SOC but it' the way it works on Linux. And the "added code"
mainly consist of adding structures, defines and generic methods for
regmap.

If it's a real problem, maybe we can introduc a new "gpcv3" driver for
i.MX8MM, i.MX8MN and i.MX8MP.

Thanks,  

Adrien Grassein (7):
  soc: imx: gpcv2: check for errors when r/w registers
  soc: imx: gpcv2: Fix power up/down sequence
  soc: imx: gpcv2: allow domains without power sequence control
  dt-bindings: power: fsl,imx-gpcv2: add definitions for i.MX8MM
  soc: imx: gpcv2: add HSIOMIX and USB domains for i.MX8MM
  soc: imx: gpcv2: add quirks to domains
  arm64: dts: imx8mm: add power-domains

 .../bindings/power/fsl,imx-gpcv2.yaml         |   7 +-
 arch/arm64/boot/dts/freescale/imx8mm.dtsi     |  35 ++
 drivers/soc/imx/gpcv2.c                       | 336 ++++++++++++++----
 include/dt-bindings/power/imx8mm-power.h      |  21 ++
 4 files changed, 333 insertions(+), 66 deletions(-)
 create mode 100644 include/dt-bindings/power/imx8mm-power.h

-- 
2.25.1