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Message-ID: <YG1zo2DApRdonUVQ@hirez.programming.kicks-ass.net>
Date: Wed, 7 Apr 2021 10:56:03 +0200
From: Peter Zijlstra <peterz@...radead.org>
To: Like Xu <like.xu@...ux.intel.com>
Cc: Sean Christopherson <seanjc@...gle.com>,
Paolo Bonzini <pbonzini@...hat.com>, eranian@...gle.com,
andi@...stfloor.org, kan.liang@...ux.intel.com,
wei.w.wang@...el.com, Wanpeng Li <wanpengli@...cent.com>,
Vitaly Kuznetsov <vkuznets@...hat.com>,
Jim Mattson <jmattson@...gle.com>,
Joerg Roedel <joro@...tes.org>, kvm@...r.kernel.org,
x86@...nel.org, linux-kernel@...r.kernel.org,
Andi Kleen <ak@...ux.intel.com>,
Luwei Kang <luwei.kang@...el.com>
Subject: Re: [PATCH v4 07/16] KVM: x86/pmu: Add IA32_PEBS_ENABLE MSR
emulation for extended PEBS
On Mon, Mar 29, 2021 at 01:41:28PM +0800, Like Xu wrote:
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index 546d6ecf0a35..9afcad882f4f 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -186,6 +186,12 @@
> #define MSR_IA32_DS_AREA 0x00000600
> #define MSR_IA32_PERF_CAPABILITIES 0x00000345
> #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6
> +#define PERF_CAP_PEBS_TRAP BIT_ULL(6)
> +#define PERF_CAP_ARCH_REG BIT_ULL(7)
> +#define PERF_CAP_PEBS_FORMAT 0xf00
> +#define PERF_CAP_PEBS_BASELINE BIT_ULL(14)
> +#define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \
> + PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE)
broken indentation
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