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Message-ID: <YG8H6Fac/p6PpcAu@hirez.programming.kicks-ass.net>
Date: Thu, 8 Apr 2021 15:40:56 +0200
From: Peter Zijlstra <peterz@...radead.org>
To: kan.liang@...ux.intel.com
Cc: mingo@...nel.org, linux-kernel@...r.kernel.org, acme@...nel.org,
tglx@...utronix.de, bp@...en8.de, namhyung@...nel.org,
jolsa@...hat.com, ak@...ux.intel.com, yao.jin@...ux.intel.com,
alexander.shishkin@...ux.intel.com, adrian.hunter@...el.com,
ricardo.neri-calderon@...ux.intel.com
Subject: Re: [PATCH V5 04/25] perf/x86/intel: Hybrid PMU support for perf
capabilities
On Mon, Apr 05, 2021 at 08:10:46AM -0700, kan.liang@...ux.intel.com wrote:
> +static inline bool intel_pmu_has_cap(struct perf_event *event, int idx)
> +{
> + union perf_capabilities *intel_cap;
> +
> + intel_cap = is_hybrid() ? &hybrid_pmu(event->pmu)->intel_cap :
> + &x86_pmu.intel_cap;
This isn't:
intel_cap = &hybrid_pmu(event->pmu)->intel_cap;
because..
> +
> + return test_bit(idx, (unsigned long *)&intel_cap->capabilities);
> +}
> @@ -3712,7 +3721,7 @@ static int intel_pmu_hw_config(struct perf_event *event)
> * with a slots event as group leader. When the slots event
> * is used in a metrics group, it too cannot support sampling.
> */
> - if (x86_pmu.intel_cap.perf_metrics && is_topdown_event(event)) {
> + if (intel_pmu_has_cap(event, PERF_CAP_METRICS_IDX) && is_topdown_event(event)) {
> if (event->attr.config1 || event->attr.config2)
> return -EINVAL;
>
> @@ -4330,7 +4347,7 @@ static int intel_pmu_check_period(struct perf_event *event, u64 value)
>
> static int intel_pmu_aux_output_match(struct perf_event *event)
> {
> - if (!x86_pmu.intel_cap.pebs_output_pt_available)
> + if (!intel_pmu_has_cap(event, PERF_CAP_PT_IDX))
> return 0;
>
> return is_intel_pt_event(event);
these sites can have !event->pmu ?
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