[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <1617862168.8874.13.camel@mtksdccf07>
Date: Thu, 8 Apr 2021 14:09:28 +0800
From: Nina Wu <nina-cm.wu@...iatek.com>
To: Matthias Brugger <matthias.bgg@...il.com>
CC: Rob Herring <robh+dt@...nel.org>,
Zhen Lei <thunder.leizhen@...wei.com>,
Neal Liu <neal.liu@...iatek.com>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-mediatek@...ts.infradead.org>,
<srv_heupstream@...iatek.com>, <Jackson-kt.Chang@...iatek.com>
Subject: Re: [PATCH v2 5/6] soc: mediatek: devapc: add debug register for
new IC support
Hi, Matthias
On Tue, 2021-04-06 at 15:53 +0200, Matthias Brugger wrote:
>
> On 01/04/2021 08:38, Nina Wu wrote:
> > From: Nina Wu <Nina-CM.Wu@...iatek.com>
> >
> > There are 3 debug info registers in new ICs while in legacy ones,
> > we have only 2. When dumping the debug info, we need to check first
> > if the 3rd debug register exists and then we can konw how to decipher
> > the debug info.
> >
> > Signed-off-by: Nina Wu <Nina-CM.Wu@...iatek.com>
> > ---
> > drivers/soc/mediatek/mtk-devapc.c | 31 +++++++++++++++++++++++++++++--
> > 1 file changed, 29 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-devapc.c
> > index bcf6e3c..af55c01 100644
> > --- a/drivers/soc/mediatek/mtk-devapc.c
> > +++ b/drivers/soc/mediatek/mtk-devapc.c
> > @@ -26,9 +26,19 @@ struct mtk_devapc_vio_dbgs {
> > u32 addr_h:4;
> > u32 resv:4;
> > } dbg0_bits;
> > +
> > + /* Not used, reference only */
> > + struct {
> > + u32 dmnid:6;
> > + u32 vio_w:1;
> > + u32 vio_r:1;
> > + u32 addr_h:4;
> > + u32 resv:20;
> > + } dbg0_bits_ver2;
> > };
> >
> > u32 vio_dbg1;
> > + u32 vio_dbg2;
> > };
> >
> > struct mtk_devapc_data {
> > @@ -37,6 +47,7 @@ struct mtk_devapc_data {
> > u32 vio_sta_offset;
> > u32 vio_dbg0_offset;
> > u32 vio_dbg1_offset;
> > + u32 vio_dbg2_offset;
> > u32 apc_con_offset;
> > u32 vio_shift_sta_offset;
> > u32 vio_shift_sel_offset;
> > @@ -158,12 +169,29 @@ static void devapc_extract_vio_dbg(struct mtk_devapc_context *ctx)
> > struct mtk_devapc_vio_dbgs vio_dbgs;
> > void __iomem *vio_dbg0_reg;
> > void __iomem *vio_dbg1_reg;
> > + void __iomem *vio_dbg2_reg;
> > + u32 vio_addr, bus_id;
> >
> > vio_dbg0_reg = ctx->base + ctx->data->vio_dbg0_offset;
> > vio_dbg1_reg = ctx->base + ctx->data->vio_dbg1_offset;
> > + vio_dbg2_reg = ctx->base + ctx->data->vio_dbg2_offset;
>
> We should read this only if we have version2 of the devapc.
>
You're right.
It is not good to read vio_dbg2_reg in version one. Even though we will
only get the value from offset 0 (which is not expected) instead of
doing any real harm. (like causing bus hang)
> >
> > vio_dbgs.vio_dbg0 = readl(vio_dbg0_reg);
> > vio_dbgs.vio_dbg1 = readl(vio_dbg1_reg);
> > + vio_dbgs.vio_dbg2 = readl(vio_dbg2_reg);
> > +
> > + if (!ctx->data->vio_dbg2_offset) {
>
> I think we should add a version field to mtk_devapc_data to distinguish the two
> of them.
OK.
I will try to add this field in the next version
>
> > + /* arch version 1 */
> > + bus_id = vio_dbgs.dbg0_bits.mstid;
> > + vio_addr = vio_dbgs.vio_dbg1;
> > + } else {
> > + /* arch version 2 */
> > + bus_id = vio_dbgs.vio_dbg1;
> > + vio_addr = vio_dbgs.vio_dbg2;
> > +
> > + /* To align with the bit definition of arch_ver 1 */
> > + vio_dbgs.vio_dbg0 = (vio_dbgs.vio_dbg0 << 16);
>
> That's magic, better add another variable domain_id and do here:
> domain_id = vio_dgbs.dbg0_bits_ver2.dmnid;
>
OK.
I will fix it up in the next version.
Thanks
> > + }
> >
> > /* Print violation information */
> > if (vio_dbgs.dbg0_bits.vio_w)
> > @@ -172,8 +200,7 @@ static void devapc_extract_vio_dbg(struct mtk_devapc_context *ctx)
> > dev_info(ctx->dev, "Read Violation\n");
> >
> > dev_info(ctx->dev, "Bus ID:0x%x, Dom ID:0x%x, Vio Addr:0x%x\n",
> > - vio_dbgs.dbg0_bits.mstid, vio_dbgs.dbg0_bits.dmnid,
> > - vio_dbgs.vio_dbg1);
> > + bus_id, vio_dbgs.dbg0_bits.dmnid, vio_addr);
> > }
> >
> > /*
> >
Powered by blists - more mailing lists