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Message-ID: <20210408094241.GA31714@Asurada-Nvidia>
Date: Thu, 8 Apr 2021 02:42:42 -0700
From: Nicolin Chen <nicoleotsuka@...il.com>
To: Dmitry Osipenko <digetx@...il.com>
Cc: Thierry Reding <thierry.reding@...il.com>,
Joerg Roedel <joro@...tes.org>,
Jonathan Hunter <jonathanh@...dia.com>,
Krishna Reddy <vdumpa@...dia.com>,
Will Deacon <will@...nel.org>,
iommu@...ts.linux-foundation.org, linux-tegra@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v1 1/2] iommu/tegra-smmu: Defer attachment of display
clients
On Mon, Mar 29, 2021 at 02:32:55AM +0300, Dmitry Osipenko wrote:
> All consumer-grade Android and Chromebook devices show a splash screen
> on boot and then display is left enabled when kernel is booted. This
> behaviour is unacceptable in a case of implicit IOMMU domains to which
> devices are attached during kernel boot since devices, like display
> controller, may perform DMA at that time. We can work around this problem
> by deferring the enable of SMMU translation for a specific devices,
> like a display controller, until the first IOMMU mapping is created,
> which works good enough in practice because by that time h/w is already
> stopped.
>
> Signed-off-by: Dmitry Osipenko <digetx@...il.com>
For both patches:
Acked-by: Nicolin Chen <nicoleotsuka@...il.com>
Tested-by: Nicolin Chen <nicoleotsuka@...il.com>
The WAR looks good to me. Perhaps Thierry would give some input.
Another topic:
I think this may help work around the mc-errors, which we have
been facing on Tegra210 also when we enable IOMMU_DOMAIN_DMA.
(attached a test patch rebasing on these two)
However, GPU would also report errors using DMA domain:
nouveau 57000000.gpu: acr: firmware unavailable
nouveau 57000000.gpu: pmu: firmware unavailable
nouveau 57000000.gpu: gr: firmware unavailable
tegra-mc 70019000.memory-controller: gpusrd: read @0x00000000fffbe200: Security violation (TrustZone violation)
nouveau 57000000.gpu: DRM: failed to create kernel channel, -22
tegra-mc 70019000.memory-controller: gpusrd: read @0x00000000fffad000: Security violation (TrustZone violation)
nouveau 57000000.gpu: fifo: SCHED_ERROR 20 []
nouveau 57000000.gpu: fifo: SCHED_ERROR 20 []
Looking at the address, seems that GPU allocated memory in 32-bit
physical address space behind SMMU, so a violation happened after
turning on DMA domain I guess...
View attachment "dma_domain.patch" of type "text/x-diff" (2397 bytes)
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