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Message-ID: <1617956377-4075-7-git-send-email-nina-cm.wu@mediatek.com>
Date: Fri, 9 Apr 2021 16:19:37 +0800
From: Nina Wu <nina-cm.wu@...iatek.com>
To: Rob Herring <robh+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>
CC: Nina Wu <Nina-CM.Wu@...iatek.com>,
Zhen Lei <thunder.leizhen@...wei.com>,
Neal Liu <neal.liu@...iatek.com>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-mediatek@...ts.infradead.org>,
<srv_heupstream@...iatek.com>, <Jackson-kt.Chang@...iatek.com>
Subject: [PATCH v3 7/7] arm64: dts: mt8192: Add devapc node
From: Nina Wu <Nina-CM.Wu@...iatek.com>
Add devapc nodes to mt8192.
Signed-off-by: Nina Wu <Nina-CM.Wu@...iatek.com>
---
This patch depends on "Add dt-bindings of MT8192 clocks" [1]
and "Add mt8192 clock controllers" [2]
[1] https://patchwork.kernel.org/project/linux-mediatek/patch/20210324104110.13383-7-chun-jie.chen@mediatek.com/
[2] https://patchwork.kernel.org/project/linux-mediatek/patch/20210331083854.7650-2-chun-jie.chen@mediatek.com/
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 36 ++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index fe24cc6..4f5fb62 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -518,6 +518,33 @@
clock-names = "clk13m";
};
+ devapc_infra: devapc@...07000 {
+ compatible = "mediatek,mt8192-devapc";
+ reg = <0 0x10207000 0 0x1000>;
+ vio-idx-num = <367>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_DEVICE_APC>;
+ clock-names = "devapc-infra-clock";
+ };
+
+ devapc_peri: devapc@...74000 {
+ compatible = "mediatek,mt8192-devapc";
+ reg = <0 0x10274000 0 0x1000>;
+ vio-idx-num = <292>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_DEVICE_APC>;
+ clock-names = "devapc-infra-clock";
+ };
+
+ devapc_peri2: devapc@...75000 {
+ compatible = "mediatek,mt8192-devapc";
+ reg = <0 0x10275000 0 0x1000>;
+ vio-idx-num = <242>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_DEVICE_APC>;
+ clock-names = "devapc-infra-clock";
+ };
+
scp_adsp: syscon@...20000 {
compatible = "mediatek,mt8192-scp_adsp", "syscon";
reg = <0 0x10720000 0 0x1000>;
@@ -662,6 +689,15 @@
status = "disabled";
};
+ devapc_peri_par: devapc@...20000 {
+ compatible = "mediatek,mt8192-devapc";
+ reg = <0 0x11020000 0 0x1000>;
+ vio-idx-num = <58>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_DEVICE_APC>;
+ clock-names = "devapc-infra-clock";
+ };
+
nor_flash: spi@...34000 {
compatible = "mediatek,mt8192-nor";
reg = <0 0x11234000 0 0xe0>;
--
2.6.4
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