linux-kernel - Re: [PATCH] PCI: dwc/intel-gw: Fix enabling the legacy PCI interrupt lines

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Message-ID: <MN2PR19MB36934176A011B86624E1EA2BB1739@MN2PR19MB3693.namprd19.prod.outlook.com>
Date:   Fri, 9 Apr 2021 10:17:12 +0000
From:   Rahul Tanwar <rtanwar@...linear.com>
To:     Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>
CC:     "robh@...nel.org" <robh@...nel.org>,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Cheol Yong Kim <ckim@...linear.com>,
        Qiming Wu <qwu@...linear.com>,
        Lei Chuan Hua <lchuanhua@...linear.com>
Subject: Re: [PATCH] PCI: dwc/intel-gw: Fix enabling the legacy PCI interrupt
 lines

On 9/4/2021 4:40 am, Martin Blumenstingl wrote:
> This email was sent from outside of MaxLinear.
> 
> Hi Lorenzo,
> 
> On Tue, Mar 23, 2021 at 12:36 PM Lorenzo Pieralisi
> <lorenzo.pieralisi@....com> wrote:
>  >
>  > On Wed, Jan 06, 2021 at 02:55:40PM +0100, Martin Blumenstingl wrote:
>  > > The legacy PCI interrupt lines need to be enabled using PCIE_APP_IRNEN
>  > > bits 13 (INTA), 14 (INTB), 15 (INTC) and 16 (INTD). The old code 
> however
>  > > was taking (for example) "13" as raw value instead of taking BIT(13).
>  > > Define the legacy PCI interrupt bits using the BIT() macro and then use
>  > > these in PCIE_APP_IRN_INT.
>  > >
>  > > Fixes: ed22aaaede44 ("PCI: dwc: intel: PCIe RC controller driver")
>  > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
>  > > ---
>  > > drivers/pci/controller/dwc/pcie-intel-gw.c | 10 ++++++----
>  > > 1 file changed, 6 insertions(+), 4 deletions(-)
>  > >
>  > > diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c 
> b/drivers/pci/controller/dwc/pcie-intel-gw.c
>  > > index 0cedd1f95f37..ae96bfbb6c83 100644
>  > > --- a/drivers/pci/controller/dwc/pcie-intel-gw.c
>  > > +++ b/drivers/pci/controller/dwc/pcie-intel-gw.c
>  > > @@ -39,6 +39,10 @@
>  > > #define PCIE_APP_IRN_PM_TO_ACK BIT(9)
>  > > #define PCIE_APP_IRN_LINK_AUTO_BW_STAT BIT(11)
>  > > #define PCIE_APP_IRN_BW_MGT BIT(12)
>  > > +#define PCIE_APP_IRN_INTA BIT(13)
>  > > +#define PCIE_APP_IRN_INTB BIT(14)
>  > > +#define PCIE_APP_IRN_INTC BIT(15)
>  > > +#define PCIE_APP_IRN_INTD BIT(16)
>  > > #define PCIE_APP_IRN_MSG_LTR BIT(18)
>  > > #define PCIE_APP_IRN_SYS_ERR_RC BIT(29)
>  > > #define PCIE_APP_INTX_OFST 12
>  > > @@ -48,10 +52,8 @@
>  > > PCIE_APP_IRN_RX_VDM_MSG | PCIE_APP_IRN_SYS_ERR_RC | \
>  > > PCIE_APP_IRN_PM_TO_ACK | PCIE_APP_IRN_MSG_LTR | \
>  > > PCIE_APP_IRN_BW_MGT | PCIE_APP_IRN_LINK_AUTO_BW_STAT | \
>  > > - (PCIE_APP_INTX_OFST + PCI_INTERRUPT_INTA) | \
>  > > - (PCIE_APP_INTX_OFST + PCI_INTERRUPT_INTB) | \
>  > > - (PCIE_APP_INTX_OFST + PCI_INTERRUPT_INTC) | \
>  > > - (PCIE_APP_INTX_OFST + PCI_INTERRUPT_INTD))
>  > > + PCIE_APP_IRN_INTA | PCIE_APP_IRN_INTB | \
>  > > + PCIE_APP_IRN_INTC | PCIE_APP_IRN_INTD)
>  > >
>  > > #define BUS_IATU_OFFSET SZ_256M
>  > > #define RESET_INTERVAL_MS 100
>  >
>  > This looks like a significant bug - which in turn raises the question
>  > on how well this driver has been tested.
> to give them the benefit of doubt: maybe only MSIs were tested
> 
>  > Dilip, can you review and ACK asap please ?
>  From "Re: MaxLinear, please maintain your drivers was Re: [PATCH]
> leds: lgm: fix gpiolib dependency" [0]:
>  > Please send any Lightning Mountain SoC related issues email to Rahul
>  > Tanwar (rtanwar@...linear.com) and I will ensure that I address the
>  > issues in a timely manner.
> so I added rtanwar@...linear.com to this email
> 
> 
> Best regards,
> Martin
> 
> 
> [0] https://lkml.org/lkml/2021/3/16/282 
> <https://lkml.org/lkml/2021/3/16/282>


Dilip has left the org. So not sure how exactly he tested it (maybe only 
MSIs). But i have confirmed it to be a bug. Thanks Martin for fixing it.

Acked-by: Rahul Tanwar <rtanwar@...linear.com>

Regards,
Rahul