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Message-ID: <20210409111345.294472-17-claudiu.beznea@microchip.com>
Date: Fri, 9 Apr 2021 14:13:37 +0300
From: Claudiu Beznea <claudiu.beznea@...rochip.com>
To: <nicolas.ferre@...rochip.com>, <alexandre.belloni@...tlin.com>,
<ludovic.desroches@...rochip.com>, <robh+dt@...nel.org>,
<linux@...linux.org.uk>
CC: <linux-arm-kernel@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
Claudiu Beznea <claudiu.beznea@...rochip.com>
Subject: [PATCH v2 16/24] dt-bindings: atmel-sysreg: add bindings for sama7g5
Add RAM controller and RAM PHY controller DT bindings.
Signed-off-by: Claudiu Beznea <claudiu.beznea@...rochip.com>
---
.../devicetree/bindings/arm/atmel-sysregs.txt | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
index 807264a78edc..7cd55a760d41 100644
--- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
@@ -45,7 +45,8 @@ RAMC SDRAM/DDR Controller required properties:
"atmel,at91sam9260-sdramc",
"atmel,at91sam9g45-ddramc",
"atmel,sama5d3-ddramc",
- "microchip,sam9x60-ddramc"
+ "microchip,sam9x60-ddramc",
+ "microchip,sama7g5-uddrc"
- reg: Should contain registers location and length
Examples:
@@ -55,6 +56,18 @@ Examples:
reg = <0xffffe800 0x200>;
};
+RAMC PHY Controller required properties:
+- compatible: Should be "microchip,sama7g5-ddr3phy", "syscon"
+- reg: Should contain registers location and length
+
+Example:
+
+ ddr3phy: ddr3phy@...04000 {
+ compatible = "microchip,sama7g5-ddr3phy", "syscon";
+ reg = <0xe3804000 0x1000>;
+ status = "okay";
+};
+
SHDWC Shutdown Controller
required properties:
--
2.25.1
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