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Message-ID: <20210413224535.30910-1-nm@ti.com>
Date: Tue, 13 Apr 2021 17:45:35 -0500
From: Nishanth Menon <nm@...com>
To: Jassi Brar <jassisinghbrar@...il.com>,
Rob Herring <robh+dt@...nel.org>
CC: <s-anna@...com>, <linux-kernel@...r.kernel.org>,
<devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, Nishanth Menon <nm@...com>
Subject: [PATCH V2] dt-bindings: mailbox: ti,secure-proxy: Convert to yaml
Convert the ti,secure-proxy to yaml for better checks and documentation.
Differences being mostly in the examples:
- I've dropped the example usage of mailbox client, it is better done in
tisci node definition
- Switched reg usage for address-cells and size-cells 1 - aligned with
schema checks as well
- included header in example for buildable example
While at this, lets make sure to support upto 100 rx threads even though
typically upto 1 threads is practically in use.
NOTE: The following checkpatch warning is generated since we do include the header
in the example, but this is a false positive warning.
WARNING: DT binding docs and includes should be a separate patch. See: Documentation/devicetree/bindings/submitting-patches.rst
Signed-off-by: Nishanth Menon <nm@...com>
---
Changes since V1: (Thanks Suman for some offline comments)
- Strengthened interrupt-names property to be on rails
- More documentation (we dont want an information loss between txt and
yaml)
- Added a max interrupts of 100, which is a rather conservative limit on
current devices, but who knows..
- Commit message updates
- compatible is a simpler const.
- interrupt-names are required property - makes no sense in not knowing
which interrupts belong to which thread irqs.
V1: https://lore.kernel.org/linux-arm-kernel/20210413171230.5872-1-nm@ti.com/
.../bindings/mailbox/ti,secure-proxy.txt | 50 ------------
.../bindings/mailbox/ti,secure-proxy.yaml | 79 +++++++++++++++++++
2 files changed, 79 insertions(+), 50 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mailbox/ti,secure-proxy.txt
create mode 100644 Documentation/devicetree/bindings/mailbox/ti,secure-proxy.yaml
diff --git a/Documentation/devicetree/bindings/mailbox/ti,secure-proxy.txt b/Documentation/devicetree/bindings/mailbox/ti,secure-proxy.txt
deleted file mode 100644
index 6c9c7daf0f5c..000000000000
--- a/Documentation/devicetree/bindings/mailbox/ti,secure-proxy.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-Texas Instruments' Secure Proxy
-========================================
-
-The Texas Instruments' secure proxy is a mailbox controller that has
-configurable queues selectable at SoC(System on Chip) integration. The
-Message manager is broken up into different address regions that are
-called "threads" or "proxies" - each instance is unidirectional and is
-instantiated at SoC integration level by system controller to indicate
-receive or transmit path.
-
-Message Manager Device Node:
-===========================
-Required properties:
---------------------
-- compatible: Shall be "ti,am654-secure-proxy"
-- reg-names target_data - Map the proxy data region
- rt - Map the realtime status region
- scfg - Map the configuration region
-- reg: Contains the register map per reg-names.
-- #mbox-cells Shall be 1 and shall refer to the transfer path
- called thread.
-- interrupt-names: Contains interrupt names matching the rx transfer path
- for a given SoC. Receive interrupts shall be of the
- format: "rx_<PID>".
-- interrupts: Contains the interrupt information corresponding to
- interrupt-names property.
-
-Example(AM654):
-------------
-
- secure_proxy: mailbox@...00000 {
- compatible = "ti,am654-secure-proxy";
- #mbox-cells = <1>;
- reg-names = "target_data", "rt", "scfg";
- reg = <0x0 0x32c00000 0x0 0x100000>,
- <0x0 0x32400000 0x0 0x100000>,
- <0x0 0x32800000 0x0 0x100000>;
- interrupt-names = "rx_011";
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- dmsc: dmsc {
- [...]
- mbox-names = "rx", "tx";
- # RX Thread ID is 11
- # TX Thread ID is 13
- mboxes= <&secure_proxy 11>,
- <&secure_proxy 13>;
- [...]
- };
diff --git a/Documentation/devicetree/bindings/mailbox/ti,secure-proxy.yaml b/Documentation/devicetree/bindings/mailbox/ti,secure-proxy.yaml
new file mode 100644
index 000000000000..08a4837fdfcc
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/ti,secure-proxy.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mailbox/ti,secure-proxy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments' Secure Proxy
+
+maintainers:
+ - Nishanth Menon <nm@...com>
+
+description: |
+ The Texas Instruments' secure proxy is a mailbox controller that has
+ configurable queues selectable at SoC(System on Chip) integration. The
+ Message manager is broken up into different address regions that are
+ called "threads" or "proxies" - each instance is unidirectional and is
+ instantiated at SoC integration level by system controller to indicate
+ receive or transmit path.
+
+properties:
+ $nodename:
+ pattern: "^mailbox@[0-9a-f]+$"
+
+ compatible:
+ const: ti,am654-secure-proxy
+
+ "#mbox-cells":
+ const: 1
+ description:
+ Contains the secure proxy thread ID used for the specific transfer path.
+
+ reg-names:
+ items:
+ - const: target_data
+ - const: rt
+ - const: scfg
+
+ reg:
+ minItems: 3
+
+ interrupt-names:
+ minItems: 1
+ maxItems: 100
+ items:
+ - pattern: "^rx_[0-9]{3}$"
+ description:
+ Contains the interrupt name information for the Rx interrupt path for
+ secure proxy thread in the form 'rx_<PID>'.
+
+ interrupts:
+ minItems: 1
+ maxItems: 100
+ description:
+ Contains the interrupt information for the Rx interrupt path for secure
+ proxy.
+
+required:
+ - compatible
+ - reg-names
+ - reg
+ - interrupt-names
+ - interrupts
+ - "#mbox-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ secure_proxy: mailbox@...00000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x32c00000 0x100000>,
+ <0x32400000 0x100000>,
+ <0x32800000 0x100000>;
+ interrupt-names = "rx_011";
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ };
--
2.31.0
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