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Message-ID: <CAJF2gTTE54rDfFeVGbc0BL7br3hy+6oN6KMFQDx5+aKPSSviKw@mail.gmail.com>
Date: Wed, 14 Apr 2021 13:54:18 +0800
From: Guo Ren <guoren@...nel.org>
To: David Laight <David.Laight@...lab.com>
Cc: Catalin Marinas <catalin.marinas@....com>,
Christoph Müllner <christophm30@...il.com>,
Peter Zijlstra <peterz@...radead.org>,
Palmer Dabbelt <palmer@...belt.com>,
Anup Patel <anup@...infault.org>,
linux-riscv <linux-riscv@...ts.infradead.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Guo Ren <guoren@...ux.alibaba.com>,
"will.deacon@....com" <will.deacon@....com>,
Arnd Bergmann <arnd@...db.de>
Subject: Re: [PATCH] riscv: locks: introduce ticket-based spinlock implementation
On Tue, Apr 13, 2021 at 6:54 PM David Laight <David.Laight@...lab.com> wrote:
>
> From: Catalin Marinas
> > Sent: 13 April 2021 11:45
> ...
> > This indeed needs some care. IIUC RISC-V has similar restrictions as arm
> > here, no load/store instructions are allowed between LR and SC. You
> > can't guarantee that the compiler won't spill some variable onto the
> > stack.
>
> You can probably never guarantee the compiler won't spill to stack.
> Especially if someone compiles with -O0.
>
> Which probably means that anything using LR/SC must be written in
> asm and the C wrappers disabled.
Agree, and cmpxchg has been widely used in Linux. I think it's the
last requirement for complex atomic API, although cmpxchg has ABA
problem:
CPU0
CPU1
=======
======
do {
old32 = load32;
*ptr32 = new32_tmp;
*ptr32 = old32;
load32 = cmpxchg(ptr32, old32, new32); //still success
} while (load32 != old32);
That means cmpxhg only cares about the result but not the middle
situation. It's different from LR/SC or AMO instructions.
>
> David
>
> -
> Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
> Registration No: 1397386 (Wales)
>
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
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