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Message-ID: <ced00596-20af-65b5-9e76-a23456215a64@linux.intel.com>
Date:   Tue, 13 Apr 2021 21:30:51 -0400
From:   "Liang, Kan" <kan.liang@...ux.intel.com>
To:     Andy Lutomirski <luto@...capital.net>
Cc:     Peter Zijlstra <peterz@...radead.org>,
        Ingo Molnar <mingo@...nel.org>,
        LKML <linux-kernel@...r.kernel.org>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Andi Kleen <ak@...ux.intel.com>,
        Mark Rutland <mark.rutland@....com>,
        Stephane Eranian <eranian@...gle.com>,
        Namhyung Kim <namhyung@...nel.org>
Subject: Re: [PATCH V3 2/2] perf/x86: Reset the dirty counter to prevent the
 leak for an RDPMC task



On 4/13/2021 8:34 PM, Andy Lutomirski wrote:
> On Tue, Apr 13, 2021 at 12:05 PM <kan.liang@...ux.intel.com> wrote:
>>
>> From: Kan Liang <kan.liang@...ux.intel.com>
>>
>> The counter value of a perf task may leak to another RDPMC task.
>> For example, a perf stat task as below is running on CPU 0.
>>
>>      perf stat -e 'branches,cycles' -- taskset -c 0 ./workload
> 
> I assume this doesn't fix the leak if the sensitive counter is systemwide?
>

Right.

> Could Intel please add proper security and ideally virtualization for
> this?  Ideally RDPMC permission would be a bitmask for all RDPMC-able
> counters, not just a single on/off switch.
> 

Yes, we are working on it.

For now, I think this patch is what we can do so far.

Thanks,
Kan

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