lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <df6c8363-baac-5d97-5b06-4bcd3163f83d@amd.com>
Date:   Thu, 15 Apr 2021 16:28:16 +0700
From:   "Suthikulpanit, Suravee" <suravee.suthikulpanit@....com>
To:     David Coe <david.coe@...e.co.uk>, linux-kernel@...r.kernel.org,
        iommu@...ts.linux-foundation.org
Cc:     joro@...tes.org, will@...nel.org, jsnitsel@...hat.com,
        pmenzel@...gen.mpg.de, Jon.Grimm@....com,
        Tj <ml.linux@...oe.vision>,
        Shuah Khan <skhan@...uxfoundation.org>,
        Alexander Monakov <amonakov@...ras.ru>,
        Alex Hung <1917203@...s.launchpad.net>
Subject: Re: [PATCH 2/2] iommu/amd: Remove performance counter
 pre-initialization test

David,

On 4/14/2021 10:33 PM, David Coe wrote:
> Hi Suravee!
> 
> I've re-run your revert+update patch on Ubuntu's latest kernel 5.11.0-14 partly to check my mailer's 'mangling' hadn't also reached the code!
> 
> There are 3 sets of results in the attachment, all for the Ryzen 2400G. The as-distributed kernel already incorporates your IOMMU RFCv3 patch.
> 
> A. As-distributed kernel (cold boot)
>     >5 retries, so no IOMMU read/write capability, no amd_iommu events.
> 
> B. As-distributed kernel (warm boot)
>     <5 retries, amd_iommu running stats show large numbers as before.
> 
> C. Revert+Update kernel
>     amd_iommu events listed and also show large hit/miss numbers.
> 
> In due course, I'll load the new (revert+update) kernel on the 4700G but won't overload your mail-box unless something unusual turns up.
> 
> Best regards,
> 

For the Ryzen 2400G, could you please try with:
- 1 event at a time
- Not more than 8 events (On your system, it has 2 banks x 4 counters/bank.
I am trying to see if this issue might be related to the counters multiplexing).

Thanks,
Suravee

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ