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Message-Id: <20210417031252.3020837-1-david.e.box@linux.intel.com>
Date: Fri, 16 Apr 2021 20:12:43 -0700
From: "David E. Box" <david.e.box@...ux.intel.com>
To: irenic.rajneesh@...il.com, david.e.box@...ux.intel.com,
hdegoede@...hat.com, mgross@...ux.intel.com,
gayatri.kammela@...el.com
Cc: platform-driver-x86@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: [PATCH V2 0/9] intel_pmc_core: Add sub-state requirements and mode
- Patch 1 and 2 remove the use of the global struct pmc_dev
- Patches 3-7 add support for reading low power mode sub-state
requirements, latching sub-state status on different low power mode
events, and displaying the sub-state residency in microseconds
- Patch 8 adds missing LTR IPs for TGL
- Patch 9 adds support for ADL-P which is based on TGL
Applied on top of latest hans-review/review-hans
Patches that changed in V2:
Patch 3: Variable name change
Patch 5: Do proper cleanup after fail
Patch 7: Debugfs write function fixes
David E. Box (4):
platform/x86: intel_pmc_core: Don't use global pmcdev in quirks
platform/x86: intel_pmc_core: Remove global struct pmc_dev
platform/x86: intel_pmc_core: Add option to set/clear LPM mode
platform/x86: intel_pmc_core: Add support for Alder Lake PCH-P
Gayatri Kammela (5):
platform/x86: intel_pmc_core: Handle sub-states generically
platform/x86: intel_pmc_core: Show LPM residency in microseconds
platform/x86: intel_pmc_core: Get LPM requirements for Tiger Lake
platform/x86: intel_pmc_core: Add requirements file to debugfs
platform/x86: intel_pmc_core: Add LTR registers for Tiger Lake
drivers/platform/x86/intel_pmc_core.c | 384 +++++++++++++++++++++++---
drivers/platform/x86/intel_pmc_core.h | 47 +++-
2 files changed, 395 insertions(+), 36 deletions(-)
base-commit: 823b31517ad3196324322804ee365d5fcff704d6
--
2.25.1
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