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Message-ID: <3e6bc055-9baa-7de8-84bf-47d2e8706e3d@web.de>
Date: Mon, 19 Apr 2021 18:10:02 +0200
From: Jan Kiszka <jan.kiszka@....de>
To: Michal Simek <michal.simek@...inx.com>,
Rajan Vaja <rajan.vaja@...inx.com>, robh+dt@...nel.org,
mark.rutland@....com, harini.katakam@...inx.com,
ulf.hansson@...aro.org, xuwei5@...ilicon.com, mripard@...nel.org,
heiko@...ech.de
Cc: devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/3] arm64: dts: xilinx: Add the clock nodes for zynqmp
On 19.04.21 17:14, Michal Simek wrote:
>
>
> On 4/19/21 1:48 PM, Jan Kiszka wrote:
>> On 19.04.21 12:52, Michal Simek wrote:
>>> Hi Jan,
>>>
>>> On 4/18/21 2:12 PM, Jan Kiszka wrote:
>>>> On 01.04.21 16:52, Jan Kiszka wrote:
>>>>> On 01.04.21 13:42, Michal Simek wrote:
>>>>>> Hi Jan,
>>>>>>
>>>>>> On 3/27/21 8:55 PM, Jan Kiszka wrote:
>>>>>>> On 07.11.19 10:44, Rajan Vaja wrote:
>>>>>>>> Add clock nodes for zynqmp based on CCF.
>>>>>>>>
>>>>>>>> Signed-off-by: Rajan Vaja <rajan.vaja@...inx.com>
>>>>>>>> ---
>>>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 222 +++++++++++++++++++++
>>>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 4 +-
>>>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 4 +-
>>>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts | 2 +-
>>>>>>>> .../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 4 +-
>>>>>>>> .../boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 4 +-
>>>>>>>> .../boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 4 +-
>>>>>>>> .../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 4 +-
>>>>>>>> .../boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 4 +-
>>>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 4 +-
>>>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 4 +-
>>>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 4 +-
>>>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 4 +-
>>>>>>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 4 +-
>>>>>>>> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 24 ++-
>>>>>>>> 15 files changed, 270 insertions(+), 26 deletions(-)
>>>>>>>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
>>>>>>>>
>>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
>>>>>>>> new file mode 100644
>>>>>>>> index 0000000..9868ca1
>>>>>>>> --- /dev/null
>>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
>>>>>>>> @@ -0,0 +1,222 @@
>>>>>>>> +// SPDX-License-Identifier: GPL-2.0+
>>>>>>>> +/*
>>>>>>>> + * Clock specification for Xilinx ZynqMP
>>>>>>>> + *
>>>>>>>> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
>>>>>>>> + *
>>>>>>>> + * Michal Simek <michal.simek@...inx.com>
>>>>>>>> + */
>>>>>>>> +
>>>>>>>> +#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
>>>>>>>> +/ {
>>>>>>>> + pss_ref_clk: pss_ref_clk {
>>>>>>>> + u-boot,dm-pre-reloc;
>>>>>>>> + compatible = "fixed-clock";
>>>>>>>> + #clock-cells = <0>;
>>>>>>>> + clock-frequency = <33333333>;
>>>>>>>> + };
>>>>>>>> +
>>>>>>>> + video_clk: video_clk {
>>>>>>>> + u-boot,dm-pre-reloc;
>>>>>>>> + compatible = "fixed-clock";
>>>>>>>> + #clock-cells = <0>;
>>>>>>>> + clock-frequency = <27000000>;
>>>>>>>> + };
>>>>>>>> +
>>>>>>>> + pss_alt_ref_clk: pss_alt_ref_clk {
>>>>>>>> + u-boot,dm-pre-reloc;
>>>>>>>> + compatible = "fixed-clock";
>>>>>>>> + #clock-cells = <0>;
>>>>>>>> + clock-frequency = <0>;
>>>>>>>> + };
>>>>>>>> +
>>>>>>>> + gt_crx_ref_clk: gt_crx_ref_clk {
>>>>>>>> + u-boot,dm-pre-reloc;
>>>>>>>> + compatible = "fixed-clock";
>>>>>>>> + #clock-cells = <0>;
>>>>>>>> + clock-frequency = <108000000>;
>>>>>>>> + };
>>>>>>>> +
>>>>>>>> + aux_ref_clk: aux_ref_clk {
>>>>>>>> + u-boot,dm-pre-reloc;
>>>>>>>> + compatible = "fixed-clock";
>>>>>>>> + #clock-cells = <0>;
>>>>>>>> + clock-frequency = <27000000>;
>>>>>>>> + };
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&can0 {
>>>>>>>> + clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&can1 {
>>>>>>>> + clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&cpu0 {
>>>>>>>> + clocks = <&zynqmp_clk ACPU>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&fpd_dma_chan1 {
>>>>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&fpd_dma_chan2 {
>>>>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&fpd_dma_chan3 {
>>>>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&fpd_dma_chan4 {
>>>>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&fpd_dma_chan5 {
>>>>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&fpd_dma_chan6 {
>>>>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&fpd_dma_chan7 {
>>>>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&fpd_dma_chan8 {
>>>>>>>> + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&lpd_dma_chan1 {
>>>>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&lpd_dma_chan2 {
>>>>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&lpd_dma_chan3 {
>>>>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&lpd_dma_chan4 {
>>>>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&lpd_dma_chan5 {
>>>>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&lpd_dma_chan6 {
>>>>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&lpd_dma_chan7 {
>>>>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&lpd_dma_chan8 {
>>>>>>>> + clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&gem0 {
>>>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
>>>>>>>> + <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
>>>>>>>> + <&zynqmp_clk GEM_TSU>;
>>>>>>>> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&gem1 {
>>>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
>>>>>>>> + <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
>>>>>>>> + <&zynqmp_clk GEM_TSU>;
>>>>>>>> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&gem2 {
>>>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
>>>>>>>> + <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
>>>>>>>> + <&zynqmp_clk GEM_TSU>;
>>>>>>>> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&gem3 {
>>>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
>>>>>>>> + <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
>>>>>>>> + <&zynqmp_clk GEM_TSU>;
>>>>>>>> + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&gpio {
>>>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&i2c0 {
>>>>>>>> + clocks = <&zynqmp_clk I2C0_REF>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&i2c1 {
>>>>>>>> + clocks = <&zynqmp_clk I2C1_REF>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&pcie {
>>>>>>>> + clocks = <&zynqmp_clk PCIE_REF>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&sata {
>>>>>>>> + clocks = <&zynqmp_clk SATA_REF>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&sdhci0 {
>>>>>>>> + clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&sdhci1 {
>>>>>>>> + clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&spi0 {
>>>>>>>> + clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&spi1 {
>>>>>>>> + clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&ttc0 {
>>>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&ttc1 {
>>>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&ttc2 {
>>>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&ttc3 {
>>>>>>>> + clocks = <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&uart0 {
>>>>>>>> + clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&uart1 {
>>>>>>>> + clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&usb0 {
>>>>>>>> + clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&usb1 {
>>>>>>>> + clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
>>>>>>>> +};
>>>>>>>> +
>>>>>>>> +&watchdog0 {
>>>>>>>> + clocks = <&zynqmp_clk WDT>;
>>>>>>>> +};
>>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
>>>>>>>> index 0f7b4cf..2e05fa4 100644
>>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
>>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
>>>>>>>> @@ -2,7 +2,7 @@
>>>>>>>> /*
>>>>>>>> * dts file for Xilinx ZynqMP ZC1232
>>>>>>>> *
>>>>>>>> - * (C) Copyright 2017 - 2018, Xilinx, Inc.
>>>>>>>> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
>>>>>>>> *
>>>>>>>> * Michal Simek <michal.simek@...inx.com>
>>>>>>>> */
>>>>>>>> @@ -10,7 +10,7 @@
>>>>>>>> /dts-v1/;
>>>>>>>>
>>>>>>>> #include "zynqmp.dtsi"
>>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>>>
>>>>>>>> / {
>>>>>>>> model = "ZynqMP ZC1232 RevA";
>>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
>>>>>>>> index 9092828..3d0aaa0 100644
>>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
>>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
>>>>>>>> @@ -2,7 +2,7 @@
>>>>>>>> /*
>>>>>>>> * dts file for Xilinx ZynqMP ZC1254
>>>>>>>> *
>>>>>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>>>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>>>>>> *
>>>>>>>> * Michal Simek <michal.simek@...inx.com>
>>>>>>>> * Siva Durga Prasad Paladugu <sivadur@...inx.com>
>>>>>>>> @@ -11,7 +11,7 @@
>>>>>>>> /dts-v1/;
>>>>>>>>
>>>>>>>> #include "zynqmp.dtsi"
>>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>>>
>>>>>>>> / {
>>>>>>>> model = "ZynqMP ZC1254 RevA";
>>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
>>>>>>>> index 4f404c5..1a8127d4 100644
>>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
>>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
>>>>>>>> @@ -11,7 +11,7 @@
>>>>>>>> /dts-v1/;
>>>>>>>>
>>>>>>>> #include "zynqmp.dtsi"
>>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>>>
>>>>>>>> / {
>>>>>>>> model = "ZynqMP ZC1275 RevA";
>>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
>>>>>>>> index 9a3e39d..fa7eb1b 100644
>>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
>>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
>>>>>>>> @@ -2,7 +2,7 @@
>>>>>>>> /*
>>>>>>>> * dts file for Xilinx ZynqMP zc1751-xm015-dc1
>>>>>>>> *
>>>>>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>>>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>>>>>> *
>>>>>>>> * Michal Simek <michal.simek@...inx.com>
>>>>>>>> */
>>>>>>>> @@ -10,7 +10,7 @@
>>>>>>>> /dts-v1/;
>>>>>>>>
>>>>>>>> #include "zynqmp.dtsi"
>>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>>>>
>>>>>>>> / {
>>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
>>>>>>>> index 2421ec7..4191dfa 100644
>>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
>>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
>>>>>>>> @@ -2,7 +2,7 @@
>>>>>>>> /*
>>>>>>>> * dts file for Xilinx ZynqMP zc1751-xm016-dc2
>>>>>>>> *
>>>>>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>>>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>>>>>> *
>>>>>>>> * Michal Simek <michal.simek@...inx.com>
>>>>>>>> */
>>>>>>>> @@ -10,7 +10,7 @@
>>>>>>>> /dts-v1/;
>>>>>>>>
>>>>>>>> #include "zynqmp.dtsi"
>>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>>>>
>>>>>>>> / {
>>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
>>>>>>>> index 7a49dee..3750690 100644
>>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
>>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
>>>>>>>> @@ -2,7 +2,7 @@
>>>>>>>> /*
>>>>>>>> * dts file for Xilinx ZynqMP zc1751-xm017-dc3
>>>>>>>> *
>>>>>>>> - * (C) Copyright 2016 - 2018, Xilinx, Inc.
>>>>>>>> + * (C) Copyright 2016 - 2019, Xilinx, Inc.
>>>>>>>> *
>>>>>>>> * Michal Simek <michal.simek@...inx.com>
>>>>>>>> */
>>>>>>>> @@ -10,7 +10,7 @@
>>>>>>>> /dts-v1/;
>>>>>>>>
>>>>>>>> #include "zynqmp.dtsi"
>>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>>>
>>>>>>>> / {
>>>>>>>> model = "ZynqMP zc1751-xm017-dc3 RevA";
>>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
>>>>>>>> index 54c7b4f..2366cd9 100644
>>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
>>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
>>>>>>>> @@ -2,7 +2,7 @@
>>>>>>>> /*
>>>>>>>> * dts file for Xilinx ZynqMP zc1751-xm018-dc4
>>>>>>>> *
>>>>>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>>>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>>>>>> *
>>>>>>>> * Michal Simek <michal.simek@...inx.com>
>>>>>>>> */
>>>>>>>> @@ -10,7 +10,7 @@
>>>>>>>> /dts-v1/;
>>>>>>>>
>>>>>>>> #include "zynqmp.dtsi"
>>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>>>
>>>>>>>> / {
>>>>>>>> model = "ZynqMP zc1751-xm018-dc4";
>>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
>>>>>>>> index b8b5ff1..9a894e6 100644
>>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
>>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
>>>>>>>> @@ -2,7 +2,7 @@
>>>>>>>> /*
>>>>>>>> * dts file for Xilinx ZynqMP zc1751-xm019-dc5
>>>>>>>> *
>>>>>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>>>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>>>>>> *
>>>>>>>> * Siva Durga Prasad <siva.durga.paladugu@...inx.com>
>>>>>>>> * Michal Simek <michal.simek@...inx.com>
>>>>>>>> @@ -11,7 +11,7 @@
>>>>>>>> /dts-v1/;
>>>>>>>>
>>>>>>>> #include "zynqmp.dtsi"
>>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>>>>
>>>>>>>> / {
>>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>>>>>>>> index e5699d0..3e39454 100644
>>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>>>>>>>> @@ -2,7 +2,7 @@
>>>>>>>> /*
>>>>>>>> * dts file for Xilinx ZynqMP ZCU100 revC
>>>>>>>> *
>>>>>>>> - * (C) Copyright 2016 - 2018, Xilinx, Inc.
>>>>>>>> + * (C) Copyright 2016 - 2019, Xilinx, Inc.
>>>>>>>> *
>>>>>>>> * Michal Simek <michal.simek@...inx.com>
>>>>>>>> * Nathalie Chan King Choy
>>>>>>>> @@ -11,7 +11,7 @@
>>>>>>>> /dts-v1/;
>>>>>>>>
>>>>>>>> #include "zynqmp.dtsi"
>>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>>> #include <dt-bindings/input/input.h>
>>>>>>>> #include <dt-bindings/interrupt-controller/irq.h>
>>>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>>>>>>>> index 2a3b665..f6e9558 100644
>>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>>>>>>>> @@ -2,7 +2,7 @@
>>>>>>>> /*
>>>>>>>> * dts file for Xilinx ZynqMP ZCU102 RevA
>>>>>>>> *
>>>>>>>> - * (C) Copyright 2015 - 2018, Xilinx, Inc.
>>>>>>>> + * (C) Copyright 2015 - 2019, Xilinx, Inc.
>>>>>>>> *
>>>>>>>> * Michal Simek <michal.simek@...inx.com>
>>>>>>>> */
>>>>>>>> @@ -10,7 +10,7 @@
>>>>>>>> /dts-v1/;
>>>>>>>>
>>>>>>>> #include "zynqmp.dtsi"
>>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>>> #include <dt-bindings/input/input.h>
>>>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>>>>
>>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
>>>>>>>> index 8f45614..f457f8a 100644
>>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
>>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
>>>>>>>> @@ -2,7 +2,7 @@
>>>>>>>> /*
>>>>>>>> * dts file for Xilinx ZynqMP ZCU104
>>>>>>>> *
>>>>>>>> - * (C) Copyright 2017 - 2018, Xilinx, Inc.
>>>>>>>> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
>>>>>>>> *
>>>>>>>> * Michal Simek <michal.simek@...inx.com>
>>>>>>>> */
>>>>>>>> @@ -10,7 +10,7 @@
>>>>>>>> /dts-v1/;
>>>>>>>>
>>>>>>>> #include "zynqmp.dtsi"
>>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>>>>
>>>>>>>> / {
>>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
>>>>>>>> index 93ce7eb..f15b99a 100644
>>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
>>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
>>>>>>>> @@ -2,7 +2,7 @@
>>>>>>>> /*
>>>>>>>> * dts file for Xilinx ZynqMP ZCU106
>>>>>>>> *
>>>>>>>> - * (C) Copyright 2016, Xilinx, Inc.
>>>>>>>> + * (C) Copyright 2016 - 2019, Xilinx, Inc.
>>>>>>>> *
>>>>>>>> * Michal Simek <michal.simek@...inx.com>
>>>>>>>> */
>>>>>>>> @@ -10,7 +10,7 @@
>>>>>>>> /dts-v1/;
>>>>>>>>
>>>>>>>> #include "zynqmp.dtsi"
>>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>>> #include <dt-bindings/input/input.h>
>>>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>>>>
>>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
>>>>>>>> index 8bb0001..e27cd60 100644
>>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
>>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
>>>>>>>> @@ -2,7 +2,7 @@
>>>>>>>> /*
>>>>>>>> * dts file for Xilinx ZynqMP ZCU111
>>>>>>>> *
>>>>>>>> - * (C) Copyright 2017 - 2018, Xilinx, Inc.
>>>>>>>> + * (C) Copyright 2017 - 2019, Xilinx, Inc.
>>>>>>>> *
>>>>>>>> * Michal Simek <michal.simek@...inx.com>
>>>>>>>> */
>>>>>>>> @@ -10,7 +10,7 @@
>>>>>>>> /dts-v1/;
>>>>>>>>
>>>>>>>> #include "zynqmp.dtsi"
>>>>>>>> -#include "zynqmp-clk.dtsi"
>>>>>>>> +#include "zynqmp-clk-ccf.dtsi"
>>>>>>>> #include <dt-bindings/input/input.h>
>>>>>>>> #include <dt-bindings/gpio/gpio.h>
>>>>>>>>
>>>>>>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>>>>>>> index 9aa6734..59a547b 100644
>>>>>>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>>>>>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>>>>>>>> @@ -2,7 +2,7 @@
>>>>>>>> /*
>>>>>>>> * dts file for Xilinx ZynqMP
>>>>>>>> *
>>>>>>>> - * (C) Copyright 2014 - 2015, Xilinx, Inc.
>>>>>>>> + * (C) Copyright 2014 - 2019, Xilinx, Inc.
>>>>>>>> *
>>>>>>>> * Michal Simek <michal.simek@...inx.com>
>>>>>>>> *
>>>>>>>> @@ -124,6 +124,28 @@
>>>>>>>> <1 10 0xf08>;
>>>>>>>> };
>>>>>>>>
>>>>>>>> + firmware {
>>>>>>>> + zynqmp_firmware: zynqmp-firmware {
>>>>>>>> + compatible = "xlnx,zynqmp-firmware";
>>>>>>>> + method = "smc";
>>>>>>>> + zynqmp_clk: clock-controller {
>>>>>>>> + u-boot,dm-pre-reloc;
>>>>>>>> + #clock-cells = <1>;
>>>>>>>> + compatible = "xlnx,zynqmp-clk";
>>>>>>>> + clocks = <&pss_ref_clk>,
>>>>>>>> + <&video_clk>,
>>>>>>>> + <&pss_alt_ref_clk>,
>>>>>>>> + <&aux_ref_clk>,
>>>>>>>> + <>_crx_ref_clk>;
>>>>>>>> + clock-names = "pss_ref_clk",
>>>>>>>> + "video_clk",
>>>>>>>> + "pss_alt_ref_clk",
>>>>>>>> + "aux_ref_clk",
>>>>>>>> + "gt_crx_ref_clk";
>>>>>>>> + };
>>>>>>>> + };
>>>>>>>> + };
>>>>>>>> +
>>>>>>>> amba_apu: amba-apu@0 {
>>>>>>>> compatible = "simple-bus";
>>>>>>>> #address-cells = <2>;
>>>>>>>>
>>>>>>>
>>>>>>> Updating my Ultra96 setups from 5.4 to 5.10, I ran into a blocker:
>>>>>>> Starting from this commit on, I'm no longer getting the kernel to boot
>>>>>>> on both revision 1 and 2 (arm64 defconfig as reference). If I switch the
>>>>>>> DTBs back before this commit, even a kernel from today's head is fine.
>>>>>>>
>>>>>>> Further versions of potential relevance:
>>>>>>> - PMUFW 2019.1 and 2020.2
>>>>>>> - TF-A 2.3
>>>>>>> - U-Boot 2020.10
>>>>>>>
>>>>>>> What's missing? I suspect someone forgot to document a subtle dependency
>>>>>>> of this change.
>>>>>>
>>>>>> Does this fix your issue?
>>>>>> https://lore.kernel.org/linux-arm-kernel/20210316090540.973014-1-punit1.agrawal@toshiba.co.jp/
>>>>>>
>>>>>
>>>>> Nope, CONFIG_COMMON_CLK_ZYNQMP=y does not help. Maybe the defconfig is
>>>>> missing even more. If you have some reference, I'm happy to try. I
>>>>> suspect that earlyprintk will also not reveal more without clocks (but I
>>>>> didn't play with that yet).
>>>>>
>>>>> Meanwhile, I'm carrying a revert of this commit and a related cleanup.
>>>>> That helps for now.
>>>>>
>>>>
>>>> OK, dependencies resolved (unfortunately the hard way): It either
>>>> requires TF-A master or latest release v2.4 + [1] and [2].
>>>>
>>>> Those TF-A commits were upstream about a year after the firmware-based
>>>> clock control hit the kernel. A note would have been nice - or better
>>>> sychronization between both upstreaming efforts.
>>>
>>> I wasn't responsible for TFA but I found this last year in Nov timeframe
>>> that none really upstream this. Right now that development is working
>>> like that. I am asking everybody to contribute upstream to have all the
>>> time upstream heads to work together.
>>> I haven't had a time to dig into this but unfortunatelly there is no
>>> feature checking mechanism on zynqmp TFA side to check if this is there
>>> or not but we are trying our best to check as much as possible but bugs
>>> happen.
>>
>> OK, I understand. Reminding of "upstream first" is part of my daily
>> business as well. :)
>>
>> And integration is generally more and more complicated with the growing
>> number of firmware services and interfaces, not only on this SOC...
>>
>>> And we are lacking space in OCM to be able to add more features to TFA
>>> anyway.
>>
>> Yeah, I know - I'm also overflowing it via the SDEI patch [1].
>
>
> I have looked at this. How are you using it now? I haven't had a chance
> to take a look at it. How do you use it and test it?
>
> We should try to minimalize amount of code and try to fit to OCM.
>
Sure - but I think this is getting too much off-topic for this thread.
Should we move the SDEI discussion to the TF-A list?
Jan
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