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Message-ID: <20210419030305.GJ1538589@yoga>
Date: Sun, 18 Apr 2021 22:03:05 -0500
From: Bjorn Andersson <bjorn.andersson@...aro.org>
To: Thara Gopinath <thara.gopinath@...aro.org>
Cc: herbert@...dor.apana.org.au, davem@...emloft.net,
ebiggers@...gle.com, ardb@...nel.org, sivaprak@...eaurora.org,
linux-crypto@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-msm@...r.kernel.org
Subject: Re: [Patch v2 3/7] crypto: qce: Add mode for rfc4309
On Sat 17 Apr 08:24 CDT 2021, Thara Gopinath wrote:
> rf4309 is the specification that uses aes ccm algorithms with IPsec
> security packets. Add a submode to identify rfc4309 ccm(aes) algorithm
> in the crypto driver.
>
Reviewed-by: Bjorn Andersson <bjorn.andersson@...aro.org>
> Signed-off-by: Thara Gopinath <thara.gopinath@...aro.org>
> ---
>
> v1->v2:
> - Moved up the QCE_ENCRYPT AND QCE_DECRYPT bit positions so that
> addition of other algorithms in future will not affect these
> macros.
>
> drivers/crypto/qce/common.h | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/crypto/qce/common.h b/drivers/crypto/qce/common.h
> index 3bc244bcca2d..b135440bf72b 100644
> --- a/drivers/crypto/qce/common.h
> +++ b/drivers/crypto/qce/common.h
> @@ -51,9 +51,11 @@
> #define QCE_MODE_CCM BIT(12)
> #define QCE_MODE_MASK GENMASK(12, 8)
>
> +#define QCE_MODE_CCM_RFC4309 BIT(13)
> +
> /* cipher encryption/decryption operations */
> -#define QCE_ENCRYPT BIT(13)
> -#define QCE_DECRYPT BIT(14)
> +#define QCE_ENCRYPT BIT(30)
> +#define QCE_DECRYPT BIT(31)
>
> #define IS_DES(flags) (flags & QCE_ALG_DES)
> #define IS_3DES(flags) (flags & QCE_ALG_3DES)
> @@ -73,6 +75,7 @@
> #define IS_CTR(mode) (mode & QCE_MODE_CTR)
> #define IS_XTS(mode) (mode & QCE_MODE_XTS)
> #define IS_CCM(mode) (mode & QCE_MODE_CCM)
> +#define IS_CCM_RFC4309(mode) ((mode) & QCE_MODE_CCM_RFC4309)
>
> #define IS_ENCRYPT(dir) (dir & QCE_ENCRYPT)
> #define IS_DECRYPT(dir) (dir & QCE_DECRYPT)
> --
> 2.25.1
>
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