linux-kernel - Re: [PATCH 2/5] misc: zynq: Add afi config driver

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Date:   Tue, 20 Apr 2021 11:17:00 -0700
From:   Randy Dunlap <rdunlap@...radead.org>
To:     Nava kishore Manne <nava.manne@...inx.com>, robh+dt@...nel.org,
        michal.simek@...inx.com, derek.kiernan@...inx.com,
        dragan.cvetic@...inx.com, arnd@...db.de,
        gregkh@...uxfoundation.org, rajan.vaja@...inx.com,
        jolly.shah@...inx.com, tejas.patel@...inx.com,
        amit.sunil.dhamne@...inx.com, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        chinnikishore369@...il.com, git@...inx.com
Subject: Re: [PATCH 2/5] misc: zynq: Add afi config driver

On 4/20/21 1:11 AM, Nava kishore Manne wrote:
> diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
> index f532c59bb59b..877b43b3377d 100644
> --- a/drivers/misc/Kconfig
> +++ b/drivers/misc/Kconfig
> @@ -445,6 +445,17 @@ config HISI_HIKEY_USB
>  	  switching between the dual-role USB-C port and the USB-A host ports
>  	  using only one USB controller.
>  
> +config ZYNQ_AFI
> +	tristate "Xilinx ZYNQ AFI support"
> +	help
> +	  Zynq AFI driver support for writing to the AFI registers
> +	  for configuring PS_PL Bus-width. Xilinx Zynq SoC connect
> +	  the PS to the programmable logic (PL) through the AXI port.
> +	  This AXI port helps to establish the data path between the
> +	  PS and PL.In-order to establish the proper communication path
> +	  between PS and PL, the AXI port data path should be configured
> +	  with the proper Bus-width values

End that last sentence with a period ('.').

thanks.
-- 
~Randy