linux-kernel - Re: [PATCH] clocksource/drivers/timer-mediatek: optimize systimer irq clear flow on Mediatek Socs

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Message-ID: <1619000227.25707.20.camel@mhfsdcap03>
Date:   Wed, 21 Apr 2021 18:17:07 +0800
From:   Fengquan Chen <fengquan.chen@...iatek.com>
To:     Evan Benn <evanbenn@...omium.org>,
        Daniel Lezcano <daniel.lezcano@...aro.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        "Matthias Brugger" <matthias.bgg@...il.com>,
        <dehui.sun@...iatek.com>
CC:     LKML <linux-kernel@...r.kernel.org>,
        "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
        <linux-arm-kernel@...ts.infradead.org>,
        "moderated list:ARM/Mediatek SoC support" 
        <linux-mediatek@...ts.infradead.org>
Subject: Re: [PATCH] clocksource/drivers/timer-mediatek: optimize systimer
 irq clear flow on Mediatek Socs

On Tue, 2021-03-23 at 11:48 +1100, Evan Benn wrote:
> On Thu, Mar 4, 2021 at 11:07 AM Fengquan Chen
> <Fengquan.Chen@...iatek.com> wrote:
> >
> > 1)ensure systimer is enabled before clear and disable interrupt, which only
> > for systimer in Mediatek Socs.
> 
> Why does the timer need to be enabled before the interrupt can be
> disabled? The datasheet I have does not suggest that this is required.
> 

Thanks for review. For systimer, you must enable timer before clear
irq,it's a hw limitation that would be easily neglected.

> >
> > 2)clear any pending timer-irq when shutdown to keep suspend flow clean,
> > when use systimer as tick-broadcast timer
> >
> > Change-Id: Ia3eda83324af2fdaf5cbb3569a9bf020a11f8009
> > Signed-off-by: Fengquan Chen <fengquan.chen@...iatek.com>
> > ---
> >  drivers/clocksource/timer-mediatek.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/clocksource/timer-mediatek.c b/drivers/clocksource/timer-mediatek.c
> > index 9318edc..9f1f095dc 100644
> > --- a/drivers/clocksource/timer-mediatek.c
> > +++ b/drivers/clocksource/timer-mediatek.c
> > @@ -75,6 +75,7 @@
> >  static void mtk_syst_ack_irq(struct timer_of *to)
> 
> This function seems to be mis-named. It does more than just ack the irq.
> 
> >  {
> >         /* Clear and disable interrupt */
> > +       writel(SYST_CON_EN, SYST_CON_REG(to));
> 
> This line seems to enable the timer and disable the interrupt.
> 
> >         writel(SYST_CON_IRQ_CLR | SYST_CON_EN, SYST_CON_REG(to));
> 
> This line acks the interrupt and enables the timer and disables the interrupt.
> Are these lines both necessary?
> Maybe this function should just ack the interrupt without changing the
> other bits.

Thanks for review. 

it's necessary.

As described above,we must enable timer before clear
irq, so here is just want to ensure irq clear successfully.

We always disable irq here, and will be re-enable in
mtk_syst_clkevt_next_event.

> 
> >  }
> >
> > @@ -111,6 +112,9 @@ static int mtk_syst_clkevt_next_event(unsigned long ticks,
> >
> >  static int mtk_syst_clkevt_shutdown(struct clock_event_device *clkevt)
> >  {
> > +       /* Clear any irq */
> > +       mtk_syst_ack_irq(to_timer_of(clkevt));
> > +
> >         /* Disable timer */
> >         writel(0, SYST_CON_REG(to_timer_of(clkevt)));
> 
> This is a third write to the same register, I believe all 3 writes can
> be combined into 1. Is that possible?

Thanks for review. 

there's a hw limitation here, we can not clear irq while timer is
disabled, and SYST_CON_EN&SYST_CON_IRQ_CLR bit must be write at the same
time or can not  write SYST_CON_IRQ_CLR bit seperately.


> 
> >
> > --
> > 1.8.1.1.dirty
> >