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Message-Id: <161901050007.1961279.2172742114670881645.b4-ty@ellerman.id.au>
Date:   Wed, 21 Apr 2021 23:08:20 +1000
From:   Michael Ellerman <patch-notifications@...erman.id.au>
To:     Athira Rajeev <atrajeev@...ux.vnet.ibm.com>, acme@...nel.org,
        linux-kernel@...r.kernel.org, linuxppc-dev@...ts.ozlabs.org,
        jolsa@...nel.org, mpe@...erman.id.au,
        linux-perf-users@...r.kernel.org
Cc:     ravi.bangoria@...ux.ibm.com, peterz@...radead.org,
        maddy@...ux.ibm.com, kjain@...ux.ibm.com, kan.liang@...ux.intel.com
Subject: Re: [PATCH V2 0/5] powerpc/perf: Export processor pipeline stage cycles information

On Mon, 22 Mar 2021 10:57:22 -0400, Athira Rajeev wrote:
> Performance Monitoring Unit (PMU) registers in powerpc exports
> number of cycles elapsed between different stages in the pipeline.
> Example, sampling registers in ISA v3.1.
> 
> This patchset implements kernel and perf tools support to expose
> these pipeline stage cycles using the sample type PERF_SAMPLE_WEIGHT_TYPE.
> 
> [...]

Patch 1 applied to powerpc/next.

[1/5] powerpc/perf: Expose processor pipeline stage cycles using PERF_SAMPLE_WEIGHT_STRUCT
      https://git.kernel.org/powerpc/c/af31fd0c9107e400a8eb89d0eafb40bb78802f79

cheers

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