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Message-Id: <20210422074851.17375-1-mohammad.athari.ismail@intel.com>
Date: Thu, 22 Apr 2021 15:48:51 +0800
From: mohammad.athari.ismail@...el.com
To: Jose Abreu <joabreu@...opsys.com>, Andrew Lunn <andrew@...n.ch>,
Heiner Kallweit <hkallweit1@...il.com>,
"David S . Miller" <davem@...emloft.net>,
Jakub Kicinski <kuba@...nel.org>,
Russell King <linux@...linux.org.uk>
Cc: Ong Boon Leong <boon.leong.ong@...el.com>,
Voon Weifeng <weifeng.voon@...el.com>, vee.khee.wong@...el.com,
netdev@...r.kernel.org, linux-kernel@...r.kernel.org,
mohammad.athari.ismail@...el.com
Subject: [PATCH net-next] net: pcs: Enable pre-emption packet for 10/100Mbps
From: Mohammad Athari Bin Ismail <mohammad.athari.ismail@...el.com>
Set VR_MII_DIG_CTRL1 bit-6(PRE_EMP) to enable pre-emption packet for
10/100Mbps by default. This setting doesn`t impact pre-emption
capability for other speeds.
Signed-off-by: Mohammad Athari Bin Ismail <mohammad.athari.ismail@...el.com>
---
drivers/net/pcs/pcs-xpcs.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c
index 944ba105cac1..2dbc1d46821e 100644
--- a/drivers/net/pcs/pcs-xpcs.c
+++ b/drivers/net/pcs/pcs-xpcs.c
@@ -66,6 +66,7 @@
/* VR_MII_DIG_CTRL1 */
#define DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW BIT(9)
+#define DW_VR_MII_DIG_CTRL1_PRE_EMP BIT(6)
/* VR_MII_AN_CTRL */
#define DW_VR_MII_AN_CTRL_TX_CONFIG_SHIFT 3
@@ -666,6 +667,10 @@ static int xpcs_config_aneg_c37_sgmii(struct mdio_xpcs_args *xpcs)
* PHY about the link state change after C28 AN is completed
* between PHY and Link Partner. There is also no need to
* trigger AN restart for MAC-side SGMII.
+ *
+ * For pre-emption, the setting is :-
+ * 1) VR_MII_DIG_CTRL1 Bit(6) [PRE_EMP] = 1b (Enable pre-emption packet
+ * for 10/100Mbps)
*/
ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL);
if (ret < 0)
@@ -686,7 +691,7 @@ static int xpcs_config_aneg_c37_sgmii(struct mdio_xpcs_args *xpcs)
if (ret < 0)
return ret;
- ret |= DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
+ ret |= (DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW | DW_VR_MII_DIG_CTRL1_PRE_EMP);
return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret);
}
--
2.17.1
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