linux-kernel - [tip: perf/core] perf/x86: Allow for 8<num_fixed

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Message-ID: <161916182610.29796.18400441270045420747.tip-bot2@tip-bot2>
Date:   Fri, 23 Apr 2021 07:10:26 -0000
From:   "tip-bot2 for Colin Ian King" <tip-bot2@...utronix.de>
To:     linux-tip-commits@...r.kernel.org
Cc:     Colin Ian King <colin.king@...onical.com>,
        "Peter Zijlstra (Intel)" <peterz@...radead.org>, x86@...nel.org,
        linux-kernel@...r.kernel.org
Subject: [tip: perf/core] perf/x86: Allow for 8<num_fixed_counters<16

The following commit has been merged into the perf/core branch of tip:

Commit-ID:     32d35c4a96ec79446f0d7be308a6eb248b507a0b
Gitweb:        https://git.kernel.org/tip/32d35c4a96ec79446f0d7be308a6eb248b507a0b
Author:        Colin Ian King <colin.king@...onical.com>
AuthorDate:    Tue, 20 Apr 2021 15:29:07 +01:00
Committer:     Peter Zijlstra <peterz@...radead.org>
CommitterDate: Fri, 23 Apr 2021 09:03:15 +02:00

perf/x86: Allow for 8<num_fixed_counters<16

The 64 bit value read from MSR_ARCH_PERFMON_FIXED_CTR_CTRL is being
bit-wise masked with the value (0x03 << i*4). However, the shifted value
is evaluated using 32 bit arithmetic, so will UB when i > 8. Fix this
by making 0x03 a ULL so that the shift is performed using 64 bit
arithmetic.

This makes the arithmetic internally consistent and preparers for the
day when hardware provides 8<num_fixed_counters<16.

Signed-off-by: Colin Ian King <colin.king@...onical.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Link: https://lkml.kernel.org/r/20210420142907.382417-1-colin.king@canonical.com
---
 arch/x86/events/core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 3fe66b7..c7fcc8d 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -278,7 +278,7 @@ bool check_hw_exists(struct pmu *pmu, int num_counters, int num_counters_fixed)
 		for (i = 0; i < num_counters_fixed; i++) {
 			if (fixed_counter_disabled(i, pmu))
 				continue;
-			if (val & (0x03 << i*4)) {
+			if (val & (0x03ULL << i*4)) {
 				bios_fail = 1;
 				val_fail = val;
 				reg_fail = reg;