linux-kernel - RE: [PATCH v9] USB: serial: cp210x: Add support for GPIOs on CP2108

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Date:   Mon, 26 Apr 2021 09:49:37 +0000
From:   Tung Pham <Tung.Pham@...abs.com>
To:     Johan Hovold <johan@...nel.org>,
        Pho Tran <photranvan0712@...il.com>
CC:     "gregkh@...uxfoundation.org" <gregkh@...uxfoundation.org>,
        "linux-usb@...r.kernel.org" <linux-usb@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Hung Nguyen <Hung.Nguyen@...abs.com>,
        Pho Tran <Pho.Tran@...abs.com>
Subject: RE: [PATCH v9] USB: serial: cp210x: Add support for GPIOs on CP2108

Dear Johan Hovold.
Thanks for your review.
I read you comment and answer you as following:

On Thu, Apr 08, 2021 at 05:36:07PM +0700, Pho Tran wrote:
> From: Pho Tran <pho.tran@...abs.com>
>
> Similar to other CP210x devices, GPIO interfaces (gpiochip) should be 
> supported for CP2108.

> +/*
> + * Quad Port Config definitions
> + * Refer to 
> +https://www.silabs.com/documents/public/application-notes/an978-cp210
> +x-usb-to-uart-api-specification.pdf
> + * for more information.
> + * CP210X_VENDOR_SPECIFIC, CP210X_GET_PORTCONFIG call reads these 
> +0x49 bytes
> + * on a CP2108 chip.
> + * CP2108 Quad Port State structure(used in Quad Port Config 
> +structure)  */ struct cp210x_quad_port_state {
> +     __le16 gpio_mode_PB0;
> +     __le16 gpio_mode_PB1;
> +     __le16 gpio_mode_PB2;
> +     __le16 gpio_mode_PB3;
> +     __le16 gpio_mode_PB4;
> +
> +
> +     __le16 gpio_lowpower_PB0;
> +     __le16 gpio_lowpower_PB1;
> +     __le16 gpio_lowpower_PB2;
> +     __le16 gpio_lowpower_PB3;
> +     __le16 gpio_lowpower_PB4;
> +
> +     __le16 gpio_latch_PB0;
> +     __le16 gpio_latch_PB1;
> +     __le16 gpio_latch_PB2;
> +     __le16 gpio_latch_PB3;
> +     __le16 gpio_latch_PB4;
> +};
> +
> +// Cp2108 Quad Port Config structure
> +struct cp210x_quad_port_config {
> +     struct cp210x_quad_port_state reset_state;
> +     struct cp210x_quad_port_state suspend_state;
> +     u8 ipdelay_IFC[4];
> +     u8 enhancedfxn_IFC[4];
> +     u8 enhancedfxn_device;
> +     u8 extclkfreq[4];
> +} __packed;

One more thing; I noticed that the layout of the other port-config structures do not match the ones used by your library API, which is what the above pdf documents (e.g. they have additional padding).

Tung Pham: the layout is correct, the document add padding bit to align data to 8 or 16 bit, we already use      __le16, so the data is aligned to 16 bit.

Did you verify that the above layout is actually correct? And did you try changing the pin functions in EEPROM and make sure that your code handles it as expected?

Tung Pham: we have tested to toggle GPIO pin in normal case, we will test the case that the gpio have alternative function in the future.

Is there any corresponding document for the actual device protocol?
Tung Pham:
You can refer to 
https://www.silabs.com/documents/public/data-sheets/cp2108-datasheet.pdf
for understanding the functionality of cp2108.
And 
https://www.silabs.com/documents/public/application-notes/AN721.pdf
for use simplicity software to configure the GPIO pin alternative function of cp2108.

Tung Pham.