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Message-ID: <CAAeT=Fzji_=m45ycm_rS6dFcp1M3yWLQAY01-s=WG-gj4znOog@mail.gmail.com>
Date: Mon, 26 Apr 2021 09:28:40 -0700
From: Reiji Watanabe <reijiw@...gle.com>
To: Ramakrishna Saripalli <rsaripal@....com>
Cc: linux-kernel@...r.kernel.org, x86@...nel.org, tglx@...utronix.de,
mingo@...hat.com, bp@...en8.de, hpa@...or.com,
Jonathan Corbet <corbet@....net>, bsd@...hat.com
Subject: Re: [v2 1/1] x86/cpufeatures: Implement Predictive Store Forwarding control.
> --- a/arch/x86/kernel/cpu/amd.c
> +++ b/arch/x86/kernel/cpu/amd.c
> @@ -1170,3 +1170,22 @@ void set_dr_addr_mask(unsigned long mask, int dr)
> break;
> }
> }
> +
> +static int __init psf_cmdline(char *str)
> +{
> + if (!boot_cpu_has(X86_FEATURE_PSFD))
> + return 0;
> +
> + if (!str)
> + return -EINVAL;
> +
> + if (!strcmp(str, "off")) {
> + x86_spec_ctrl_base |= SPEC_CTRL_PSFD;
> + wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
> + setup_clear_cpu_cap(X86_FEATURE_PSFD);
Shouldn't X86_FEATURE_MSR_SPEC_CTRL be set if the CPU supports PSF ?
x86_spec_ctrl_setup_ap(), which is called on non-boot CPUs, doesn't
update MSR_IA32_SPEC_CTRL with x86_spec_ctrl_base not having
X86_FEATURE_MSR_SPEC_CTRL (i.e. if a CPU supports PSF but no other
existing feature that makes the kernel set X86_FEATURE_MSR_SPEC_CTRL).
Also, since check_bugs() reads the SPEC_CTRL MSR to account for reserved
bits which may have unknown bits to set x86_spec_ctrl_base
(if X86_FEATURE_MSR_SPEC_CTRL is set),
I'm wondering if psf_cmdline(), which is called earlier
than check_bugs(), should do the same instead of overwriting
it with x86_spec_ctrl_base | SPEC_CTRL_PSFD.
Thanks,
Reiji
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