linux-kernel - Re: [v3 1/1] x86/cpufeatures: Implement Predictive Store Forwarding control.

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Message-ID: <CAAeT=FyqjYqcUBRtvCiHv5sUN34kdi7kTfbfUfHZ6jR0tve+Og@mail.gmail.com>
Date:   Wed, 28 Apr 2021 22:38:39 -0700
From:   Reiji Watanabe <reijiw@...gle.com>
To:     Ramakrishna Saripalli <rsaripal@....com>
Cc:     linux-kernel@...r.kernel.org, x86@...nel.org, tglx@...utronix.de,
        mingo@...hat.com, bp@...en8.de, hpa@...or.com,
        Jonathan Corbet <corbet@....net>, bsd@...hat.com
Subject: Re: [v3 1/1] x86/cpufeatures: Implement Predictive Store Forwarding control.

> +       if (!strcmp(str, "off")) {
> +               set_cpu_cap(&boot_cpu_data, X86_FEATURE_MSR_SPEC_CTRL);
> +               x86_spec_ctrl_base |= SPEC_CTRL_PSFD;
> +               wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);

My previous suggestion about updating MSR_IA32_SPEC_CTRL meant
something like:

    rdmsrl(MSR_IA32_SPEC_CTRL, current);
    wrmsrl(MSR_IA32_SPEC_CTRL, current | SPEC_CTRL_PSFD);

And this is to keep the behavior of code below check_bugs().
(Or do you intentionally change it due to some reason ?)
BTW, x86_spec_ctrl_base, which is updated in psf_cmdline(),
would be overwritten by check_bugs() anyway as follows.
---
void __init check_bugs(void)
{
        <...>
        /*
         * Read the SPEC_CTRL MSR to account for reserved bits which may
         * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
         * init code as it is not enumerated and depends on the family.
         */
        if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
                rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
        <...>
---

> +               setup_clear_cpu_cap(X86_FEATURE_PSFD);

Does X86_FEATURE_PSFD need to be cleared for the 'off' case ?
Do you want to remove "psfd" from /proc/cpuinfo
when PSFD is enabled ? (not when PSFD is disabled ?)


Thanks,
Reiji