linux-kernel - Re: [PATCH 14/16] soc: imx: gpcv2: move reset assert after requesting domain power up

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Date:   Fri, 30 Apr 2021 12:51:09 +0800
From:   "Peng Fan (OSS)" <peng.fan@....nxp.com>
To:     Lucas Stach <l.stach@...gutronix.de>, robh+dt@...nel.org,
        shawnguo@...nel.org, s.hauer@...gutronix.de
Cc:     kernel@...gutronix.de, festevam@...il.com, linux-imx@....com,
        p.zabel@...gutronix.de, krzk@...nel.org, agx@...xcpu.org,
        marex@...x.de, andrew.smirnov@...il.com,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org, ping.bai@....com,
        frieder.schrempf@...tron.de, aford173@...il.com, abel.vesa@....com,
        Peng Fan <peng.fan@....com>
Subject: Re: [PATCH 14/16] soc: imx: gpcv2: move reset assert after requesting
 domain power up



On 2021/4/29 22:28, Lucas Stach wrote:
> Am Donnerstag, dem 29.04.2021 um 15:30 +0800 schrieb Peng Fan (OSS):
>> From: Peng Fan <peng.fan@....com>
>>
>> The i.MX8MM VPU power up sequence is a bit special, it must follow:
>> 1. request power up
>> 2. reset assert
>> 3. reset deassert
>>
>> This change in this patch will not affect other domains, because
>> the power domain default is in asserted state, unless bootloader
>> deassert the reset.
>>
>> [Note: We expect bootloader leave the domain in asserted state,
>> but this may not always be true, so we might need another solution
>> to address the VPU domain requirements]
> 
> This is only about the VPU and GPU domain, where we need to handle the
> SRC reset from the GPC driver right?

For GPU, I have not tried. From current ATF implementation, I think yes.

  In that case I think it's a sane
> assumption that the bootloader does not touch those resets.
> 
>> Signed-off-by: Peng Fan <peng.fan@....com>
>> ---
>>   drivers/soc/imx/gpcv2.c | 4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
>> index d2ce47a5ebad..072f519462a5 100644
>> --- a/drivers/soc/imx/gpcv2.c
>> +++ b/drivers/soc/imx/gpcv2.c
>> @@ -217,8 +217,6 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
>>   		goto out_regulator_disable;
>>   	}
>>   
>>
>>
>>
>>
>>
>>
>>
>> -	reset_control_assert(domain->reset);
>> -
>>   	if (domain->bits.pxx) {
>>   		/* request the domain to power up */
>>   		regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
>> @@ -241,6 +239,8 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
>>   				   GPC_PGC_CTRL_PCR, 0);
>>   	}
>>   
>>
>>
>>
>>
>>
>>
>>
>> +	reset_control_assert(domain->reset);
>> +
>>   	/* delay for reset to propagate */
>>   	udelay(5);
> 
> As this is a pretty arbitrary delay added by me, can you please check
> with the HW team or whoever knows, if this is sufficiently long for
> both GPU and VPU domains?

For VPU, from my test, it is enough. For GPU, ATF code use 10us, let me
try to enable GPU and do some test, I think 5us is long enough here.

Thanks,
Peng.

> 
> Regards,
> Lucas
>