[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <YJEWWbEeDm0rUyC+@hirez.programming.kicks-ass.net>
Date: Tue, 4 May 2021 11:39:37 +0200
From: Peter Zijlstra <peterz@...radead.org>
To: Suravee Suthikulpanit <suravee.suthikulpanit@....com>
Cc: linux-kernel@...r.kernel.org, linux-perf-users@...r.kernel.org,
iommu@...ts.linux-foundation.org, mingo@...hat.com,
joro@...tes.org, Jon.Grimm@....com, amonakov@...ras.ru,
David Coe <david.coe@...e.co.uk>
Subject: Re: [PATCH] x86/events/amd/iommu: Fix invalid Perf result due to
IOMMU PMC power-gating
On Tue, May 04, 2021 at 01:52:36AM -0500, Suravee Suthikulpanit wrote:
> 2. Since AMD IOMMU PMU does not support interrupt mode, the logic
> can be simplified to always start counting with value zero,
> and accumulate the counter value when stopping without the need
> to keep track and reprogram the counter with the previously read
> counter value.
This relies on the hardware counter being the full 64bit wide, is it?
Powered by blists - more mailing lists