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Message-Id: <20210504105940.100004-7-greentime.hu@sifive.com>
Date: Tue, 4 May 2021 18:59:40 +0800
From: Greentime Hu <greentime.hu@...ive.com>
To: greentime.hu@...ive.com, paul.walmsley@...ive.com, hes@...ive.com,
erik.danie@...ive.com, zong.li@...ive.com, bhelgaas@...gle.com,
robh+dt@...nel.org, aou@...s.berkeley.edu, mturquette@...libre.com,
sboyd@...nel.org, lorenzo.pieralisi@....com,
p.zabel@...gutronix.de, alex.dewar90@...il.com,
khilman@...libre.com, hayashi.kunihiko@...ionext.com,
vidyas@...dia.com, jh80.chung@...sung.com,
linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org, helgaas@...nel.org
Cc: Palmer Dabbelt <palmerdabbelt@...gle.com>
Subject: [PATCH v6 6/6] riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC
Signed-off-by: Greentime Hu <greentime.hu@...ive.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@...gle.com>
---
arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 33 ++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
index eeb4f8c3e0e7..8eef82e4199f 100644
--- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
@@ -159,6 +159,7 @@ prci: clock-controller@...00000 {
reg = <0x0 0x10000000 0x0 0x1000>;
clocks = <&hfclk>, <&rtcclk>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
uart0: serial@...10000 {
compatible = "sifive,fu740-c000-uart", "sifive,uart0";
@@ -289,5 +290,37 @@ gpio: gpio@...60000 {
clocks = <&prci PRCI_CLK_PCLK>;
status = "disabled";
};
+ pcie@...000000 {
+ compatible = "sifive,fu740-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ reg = <0xe 0x00000000 0x0 0x80000000>,
+ <0xd 0xf0000000 0x0 0x10000000>,
+ <0x0 0x100d0000 0x0 0x1000>;
+ reg-names = "dbi", "config", "mgmt";
+ device_type = "pci";
+ dma-coherent;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */
+ <0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */
+ <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000>, /* mem */
+ <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */
+ num-lanes = <0x8>;
+ interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>;
+ interrupt-names = "msi", "inta", "intb", "intc", "intd";
+ interrupt-parent = <&plic0>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
+ <0x0 0x0 0x0 0x2 &plic0 58>,
+ <0x0 0x0 0x0 0x3 &plic0 59>,
+ <0x0 0x0 0x0 0x4 &plic0 60>;
+ clock-names = "pcie_aux";
+ clocks = <&prci PRCI_CLK_PCIE_AUX>;
+ pwren-gpios = <&gpio 5 0>;
+ reset-gpios = <&gpio 8 0>;
+ resets = <&prci 4>;
+ status = "okay";
+ };
};
};
--
2.31.1
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