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Message-ID: <ae801539-592a-af9a-55a1-3a4b8309ff1e@redhat.com>
Date: Tue, 4 May 2021 23:12:12 +0200
From: Paolo Bonzini <pbonzini@...hat.com>
To: Maxim Levitsky <mlevitsk@...hat.com>,
Thomas Gleixner <tglx@...utronix.de>,
Lai Jiangshan <jiangshanlai@...il.com>,
linux-kernel@...r.kernel.org
Cc: Lai Jiangshan <laijs@...ux.alibaba.com>,
Sean Christopherson <seanjc@...gle.com>,
Steven Rostedt <rostedt@...dmis.org>,
Andi Kleen <ak@...ux.intel.com>,
Andy Lutomirski <luto@...nel.org>,
Vitaly Kuznetsov <vkuznets@...hat.com>,
Wanpeng Li <wanpengli@...cent.com>,
Jim Mattson <jmattson@...gle.com>,
Joerg Roedel <joro@...tes.org>,
Josh Poimboeuf <jpoimboe@...hat.com>,
Uros Bizjak <ubizjak@...il.com>,
Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
x86@...nel.org, "H. Peter Anvin" <hpa@...or.com>,
Peter Zijlstra <peterz@...radead.org>,
Alexandre Chartre <alexandre.chartre@...cle.com>,
Juergen Gross <jgross@...e.com>,
Joerg Roedel <jroedel@...e.de>, Jian Cai <caij2003@...il.com>
Subject: Re: [PATCH] KVM/VMX: Invoke NMI non-IST entry instead of IST entry
On 04/05/21 23:05, Maxim Levitsky wrote:
> Does this mean that we still rely on hardware NMI masking to be activated?
No, the NMI code already handles reentrancy at both the assembly and C
levels.
> Or in other words, that is we still can't have an IRET between VM exit and
> the entry to the NMI handler?
No, because NMIs are not masked on VM exit. This in fact makes things
potentially messy; unlike with AMD's CLGI/STGI, only MSRs and other
things that Intel thought can be restored atomically with the VM exit.
Paolo
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