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Message-ID: <6b4eb1ae-f87c-8947-5921-62da42b7e662@kontron.de>
Date: Thu, 6 May 2021 08:36:41 +0200
From: Frieder Schrempf <frieder.schrempf@...tron.de>
To: "Peng Fan (OSS)" <peng.fan@....nxp.com>, robh+dt@...nel.org,
shawnguo@...nel.org, s.hauer@...gutronix.de
Cc: kernel@...gutronix.de, festevam@...il.com, linux-imx@....com,
p.zabel@...gutronix.de, l.stach@...gutronix.de, krzk@...nel.org,
agx@...xcpu.org, marex@...x.de, andrew.smirnov@...il.com,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, ping.bai@....com, aford173@...il.com,
abel.vesa@....com, Peng Fan <peng.fan@....com>
Subject: Re: [PATCH V2 04/13] soc: imx: gpcv2: split power up and power down
sequence control
On 06.05.21 03:04, Peng Fan (OSS) wrote:
> From: Lucas Stach <l.stach@...gutronix.de>
>
> The current mixed function to control both power up and power down
> sequences is very hard to follow and already contains some sequence
> errors like triggering the ADB400 handshake at the wrong time due to
> this. Split the function into two, which results in slightly more
> code, but is way easier to get right.
>
> Signed-off-by: Lucas Stach <l.stach@...gutronix.de>
> Signed-off-by: Peng Fan <peng.fan@....com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@...tron.de>
> ---
> drivers/soc/imx/gpcv2.c | 141 ++++++++++++++++++++++++----------------
> 1 file changed, 86 insertions(+), 55 deletions(-)
>
> diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
> index 4222b6e87e7c..bcf1f338b0bf 100644
> --- a/drivers/soc/imx/gpcv2.c
> +++ b/drivers/soc/imx/gpcv2.c
> @@ -125,20 +125,19 @@ struct imx_pgc_domain_data {
> const struct regmap_access_table *reg_access_table;
> };
>
> -static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
> - bool on)
> +static inline struct imx_pgc_domain *
> +to_imx_pgc_domain(struct generic_pm_domain *genpd)
> {
> - struct imx_pgc_domain *domain = container_of(genpd,
> - struct imx_pgc_domain,
> - genpd);
> - unsigned int offset = on ?
> - GPC_PU_PGC_SW_PUP_REQ : GPC_PU_PGC_SW_PDN_REQ;
> - const bool enable_power_control = !on;
> - const bool has_regulator = !IS_ERR(domain->regulator);
> - int i, ret = 0;
> - u32 pxx_req;
> -
> - if (has_regulator && on) {
> + return container_of(genpd, struct imx_pgc_domain, genpd);
> +}
> +
> +static int imx_pgc_power_up(struct generic_pm_domain *genpd)
> +{
> + struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
> + u32 reg_val;
> + int ret;
> +
> + if (!IS_ERR(domain->regulator)) {
> ret = regulator_enable(domain->regulator);
> if (ret) {
> dev_err(domain->dev, "failed to enable regulator\n");
> @@ -150,69 +149,101 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
> ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
> if (ret) {
> dev_err(domain->dev, "failed to enable reset clocks\n");
> - regulator_disable(domain->regulator);
> - return ret;
> + goto out_regulator_disable;
> }
>
> - if (enable_power_control)
> - regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
> - GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
> -
> - if (domain->bits.hsk)
> - regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
> - domain->bits.hsk, on ? domain->bits.hsk : 0);
> -
> - regmap_update_bits(domain->regmap, offset,
> + /* request the domain to power up */
> + regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
> domain->bits.pxx, domain->bits.pxx);
> -
> /*
> * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
> * for PUP_REQ/PDN_REQ bit to be cleared
> */
> - ret = regmap_read_poll_timeout(domain->regmap, offset, pxx_req,
> - !(pxx_req & domain->bits.pxx),
> + ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
> + reg_val, !(reg_val & domain->bits.pxx),
> 0, USEC_PER_MSEC);
> if (ret) {
> dev_err(domain->dev, "failed to command PGC\n");
> - /*
> - * If we were in a process of enabling a
> - * domain and failed we might as well disable
> - * the regulator we just enabled. And if it
> - * was the opposite situation and we failed to
> - * power down -- keep the regulator on
> - */
> - on = !on;
> + goto out_clk_disable;
> }
>
> - if (enable_power_control)
> - regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
> - GPC_PGC_CTRL_PCR, 0);
> + /* disable power control */
> + regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
> + GPC_PGC_CTRL_PCR);
> +
> + /* request the ADB400 to power up */
> + if (domain->bits.hsk)
> + regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
> + domain->bits.hsk, domain->bits.hsk);
>
> /* Disable reset clocks for all devices in the domain */
> clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
>
> - if (has_regulator && !on) {
> - int err;
> + return 0;
>
> - err = regulator_disable(domain->regulator);
> - if (err)
> - dev_err(domain->dev,
> - "failed to disable regulator: %d\n", err);
> - /* Preserve earlier error code */
> - ret = ret ?: err;
> - }
> +out_clk_disable:
> + clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
> +out_regulator_disable:
> + if (!IS_ERR(domain->regulator))
> + regulator_disable(domain->regulator);
>
> return ret;
> }
>
> -static int imx_gpc_pu_pgc_sw_pup_req(struct generic_pm_domain *genpd)
> +static int imx_pgc_power_down(struct generic_pm_domain *genpd)
> {
> - return imx_gpc_pu_pgc_sw_pxx_req(genpd, true);
> -}
> + struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
> + u32 reg_val;
> + int ret;
>
> -static int imx_gpc_pu_pgc_sw_pdn_req(struct generic_pm_domain *genpd)
> -{
> - return imx_gpc_pu_pgc_sw_pxx_req(genpd, false);
> + /* Enable reset clocks for all devices in the domain */
> + ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
> + if (ret) {
> + dev_err(domain->dev, "failed to enable reset clocks\n");
> + return ret;
> + }
> +
> + /* request the ADB400 to power down */
> + if (domain->bits.hsk)
> + regmap_clear_bits(domain->regmap, GPC_PU_PWRHSK,
> + domain->bits.hsk);
> +
> + /* enable power control */
> + regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
> + GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
> +
> + /* request the domain to power down */
> + regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ,
> + domain->bits.pxx, domain->bits.pxx);
> + /*
> + * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
> + * for PUP_REQ/PDN_REQ bit to be cleared
> + */
> + ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PGC_SW_PDN_REQ,
> + reg_val, !(reg_val & domain->bits.pxx),
> + 0, USEC_PER_MSEC);
> + if (ret) {
> + dev_err(domain->dev, "failed to command PGC\n");
> + goto out_clk_disable;
> + }
> +
> + /* Disable reset clocks for all devices in the domain */
> + clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
> +
> + if (!IS_ERR(domain->regulator)) {
> + ret = regulator_disable(domain->regulator);
> + if (ret) {
> + dev_err(domain->dev, "failed to disable regulator\n");
> + return ret;
> + }
> + }
> +
> + return 0;
> +
> +out_clk_disable:
> + clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
> +
> + return ret;
> }
>
> static const struct imx_pgc_domain imx7_pgc_domains[] = {
> @@ -590,8 +621,8 @@ static int imx_gpcv2_probe(struct platform_device *pdev)
>
> domain = pd_pdev->dev.platform_data;
> domain->regmap = regmap;
> - domain->genpd.power_on = imx_gpc_pu_pgc_sw_pup_req;
> - domain->genpd.power_off = imx_gpc_pu_pgc_sw_pdn_req;
> + domain->genpd.power_on = imx_pgc_power_up;
> + domain->genpd.power_off = imx_pgc_power_down;
>
> pd_pdev->dev.parent = dev;
> pd_pdev->dev.of_node = np;
>
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