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Message-Id: <7ce705fedac1b2b8e3a2f4013e04244dc5946344.1620641808.git.leonro@nvidia.com>
Date: Mon, 10 May 2021 13:23:33 +0300
From: Leon Romanovsky <leon@...nel.org>
To: Doug Ledford <dledford@...hat.com>,
Jason Gunthorpe <jgg@...dia.com>
Cc: Sergey Gorenko <sergeygo@...dia.com>,
Evgenii Kochetov <evgeniik@...dia.com>,
linux-kernel@...r.kernel.org, linux-rdma@...r.kernel.org
Subject: [PATCH rdma-next 2/2] RDMA/mlx5: Add SQD2RTS bit to the alloc ucontext response
From: Sergey Gorenko <sergeygo@...dia.com>
The new bit in the comp_mask is needed to mark that kernel supports
SQD2RTS transition for the modify QP command.
Reviewed-by: Evgenii Kochetov <evgeniik@...dia.com>
Signed-off-by: Sergey Gorenko <sergeygo@...dia.com>
Signed-off-by: Leon Romanovsky <leonro@...dia.com>
---
drivers/infiniband/hw/mlx5/main.c | 4 ++++
include/uapi/rdma/mlx5-abi.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/drivers/infiniband/hw/mlx5/main.c b/drivers/infiniband/hw/mlx5/main.c
index 6d1dd09a4388..312aa731860d 100644
--- a/drivers/infiniband/hw/mlx5/main.c
+++ b/drivers/infiniband/hw/mlx5/main.c
@@ -1817,6 +1817,10 @@ static int set_ucontext_resp(struct ib_ucontext *uctx,
resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE;
resp->num_dyn_bfregs = bfregi->num_dyn_bfregs;
+
+ if (MLX5_CAP_GEN(dev->mdev, drain_sigerr))
+ resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS;
+
return 0;
}
diff --git a/include/uapi/rdma/mlx5-abi.h b/include/uapi/rdma/mlx5-abi.h
index 27905a0268c9..995faf8f44bd 100644
--- a/include/uapi/rdma/mlx5-abi.h
+++ b/include/uapi/rdma/mlx5-abi.h
@@ -101,6 +101,7 @@ enum mlx5_ib_alloc_ucontext_resp_mask {
MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY = 1UL << 1,
MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE = 1UL << 2,
+ MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS = 1UL << 3,
};
enum mlx5_user_cmds_supp_uhw {
--
2.31.1
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