linux-kernel - [PATCH] mmc: sdhci-pci-gli: Fine tune GL9763E L1 entry delay

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Message-Id: <20210511061835.5559-1-benchuanggli@gmail.com>
Date:   Tue, 11 May 2021 14:18:35 +0800
From:   Ben Chuang <benchuanggli@...il.com>
To:     ulf.hansson@...aro.org, adrian.hunter@...el.com
Cc:     linux-mmc@...r.kernel.org, linux-kernel@...r.kernel.org,
        renius.chen@...esyslogic.com.tw, ben.chuang@...esyslogic.com.tw,
        seanhy.chen@...esyslogic.com.tw, greg.tu@...esyslogic.com.tw,
        totti.yan@...esyslogic.com.tw, Ben Chuang <benchuanggli@...il.com>
Subject: [PATCH] mmc: sdhci-pci-gli: Fine tune GL9763E L1 entry delay

Fine tune the value to 21us in order to improve read/write performance.

Signed-off-by: Ben Chuang <benchuanggli@...il.com>
---
 drivers/mmc/host/sdhci-pci-gli.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
index 592d79082f58..73e01c3480a3 100644
--- a/drivers/mmc/host/sdhci-pci-gli.c
+++ b/drivers/mmc/host/sdhci-pci-gli.c
@@ -94,7 +94,7 @@
 
 #define PCIE_GLI_9763E_CFG2      0x8A4
 #define   GLI_9763E_CFG2_L1DLY     GENMASK(28, 19)
-#define   GLI_9763E_CFG2_L1DLY_MID 0x50
+#define   GLI_9763E_CFG2_L1DLY_MID 0x54
 
 #define PCIE_GLI_9763E_MMC_CTRL  0x960
 #define   GLI_9763E_HS400_SLOW     BIT(3)
@@ -842,7 +842,7 @@ static void gli_set_gl9763e(struct sdhci_pci_slot *slot)
 
 	pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value);
 	value &= ~GLI_9763E_CFG2_L1DLY;
-	/* set ASPM L1 entry delay to 20us */
+	/* set ASPM L1 entry delay to 21us */
 	value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID);
 	pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value);
 
-- 
2.31.1