[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20210511005531.1065536-2-hpa@zytor.com>
Date: Mon, 10 May 2021 17:55:26 -0700
From: "H. Peter Anvin" <hpa@...or.com>
To: Ingo Molnar <mingo@...hat.com>,
Thomas Gleixner <tglx@...utronix.de>,
Borislav Petkov <bp@...en8.de>,
Andy Lutomirski <luto@...nel.org>
Cc: Steve Wahl <steve.wahl@....com>, Mike Travis <mike.travis@....com>,
Dimitri Sivanich <dimitri.sivanich@....com>,
Russ Anderson <russ.anderson@....com>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
"H. Peter Anvin (Intel)" <hpa@...or.com>
Subject: [PATCH 1/6] x86/traps: add X86_NR_HW_TRAPS to <asm/trapnr.h>
From: "H. Peter Anvin (Intel)" <hpa@...or.com>
The x86 architecture supports up to 32 trap vectors. Add that constant
to <asm/trapnr.h>.
Signed-off-by: H. Peter Anvin (Intel) <hpa@...or.com>
---
arch/x86/include/asm/trapnr.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/include/asm/trapnr.h b/arch/x86/include/asm/trapnr.h
index f5d2325aa0b7..f0baf92da20b 100644
--- a/arch/x86/include/asm/trapnr.h
+++ b/arch/x86/include/asm/trapnr.h
@@ -27,6 +27,7 @@
#define X86_TRAP_VE 20 /* Virtualization Exception */
#define X86_TRAP_CP 21 /* Control Protection Exception */
#define X86_TRAP_VC 29 /* VMM Communication Exception */
+#define X86_NR_HW_TRAPS 32 /* Max hardware trap number */
#define X86_TRAP_IRET 32 /* IRET Exception */
#endif
--
2.31.1
Powered by blists - more mailing lists