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Message-ID: <202105121620.53PlsUyv-lkp@intel.com>
Date: Wed, 12 May 2021 16:31:43 +0800
From: kernel test robot <lkp@...el.com>
To: Sean Anderson <sean.anderson@...o.com>, linux-pwm@...r.kernel.org,
devicetree@...r.kernel.org
Cc: kbuild-all@...ts.01.org, michal.simek@...inx.com,
Alvaro Gamez <alvaro.gamez@...ent.com>,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
Sean Anderson <sean.anderson@...o.com>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Lee Jones <lee.jones@...aro.org>,
Thierry Reding <thierry.reding@...il.com>
Subject: Re: [PATCH v3 2/2] clocksource: Add support for Xilinx AXI Timer
Hi Sean,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on tip/timers/core]
[also build test ERROR on pwm/for-next linux/master linus/master v5.13-rc1 next-20210511]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Sean-Anderson/dt-bindings-pwm-Add-Xilinx-AXI-Timer/20210512-031347
base: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git 2d036dfa5f10df9782f5278fc591d79d283c1fad
config: mips-randconfig-r012-20210512 (attached as .config)
compiler: mips64el-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/8e9195e8da4d8ea7fd88d14fd95d95ba21008aef
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Sean-Anderson/dt-bindings-pwm-Add-Xilinx-AXI-Timer/20210512-031347
git checkout 8e9195e8da4d8ea7fd88d14fd95d95ba21008aef
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross W=1 ARCH=mips
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@...el.com>
All error/warnings (new ones prefixed by >>):
drivers/clocksource/timer-xilinx.c: In function 'xilinx_ioread32be':
>> drivers/clocksource/timer-xilinx.c:136:20: warning: passing argument 1 of 'ioread32be' discards 'volatile' qualifier from pointer target type [-Wdiscarded-qualifiers]
136 | return ioread32be(addr);
| ^~~~
In file included from arch/mips/include/asm/io.h:28,
from arch/mips/include/asm/mmiowb.h:5,
from include/linux/spinlock.h:61,
from include/linux/rwsem.h:16,
from include/linux/notifier.h:15,
from include/linux/clk.h:14,
from drivers/clocksource/timer-xilinx.c:16:
include/asm-generic/iomap.h:33:32: note: expected 'const void *' but argument is of type 'const volatile void *'
33 | extern unsigned int ioread32be(const void __iomem *);
| ^~~~~~~~~~~~~~~~~~~~
drivers/clocksource/timer-xilinx.c: In function 'xilinx_iowrite32be':
>> drivers/clocksource/timer-xilinx.c:141:21: warning: passing argument 2 of 'iowrite32be' discards 'volatile' qualifier from pointer target type [-Wdiscarded-qualifiers]
141 | iowrite32be(value, addr);
| ^~~~
In file included from arch/mips/include/asm/io.h:28,
from arch/mips/include/asm/mmiowb.h:5,
from include/linux/spinlock.h:61,
from include/linux/rwsem.h:16,
from include/linux/notifier.h:15,
from include/linux/clk.h:14,
from drivers/clocksource/timer-xilinx.c:16:
include/asm-generic/iomap.h:54:30: note: expected 'void *' but argument is of type 'volatile void *'
54 | extern void iowrite32be(u32, void __iomem *);
| ^~~~~~~~~~~~~~
drivers/clocksource/timer-xilinx.c: In function 'xilinx_timer_init':
>> drivers/clocksource/timer-xilinx.c:447:13: error: assignment to 'u32 (*)(const volatile void *)' {aka 'unsigned int (*)(const volatile void *)'} from incompatible pointer type 'unsigned int (*)(const void *)' [-Werror=incompatible-pointer-types]
447 | priv->read = ioread32;
| ^
>> drivers/clocksource/timer-xilinx.c:448:14: error: assignment to 'void (*)(u32, volatile void *)' {aka 'void (*)(unsigned int, volatile void *)'} from incompatible pointer type 'void (*)(u32, void *)' {aka 'void (*)(unsigned int, void *)'} [-Werror=incompatible-pointer-types]
448 | priv->write = iowrite32;
| ^
cc1: some warnings being treated as errors
vim +447 drivers/clocksource/timer-xilinx.c
425
426 static struct xilinx_timer_priv *xilinx_timer_init(struct device *dev,
427 struct device_node *np)
428 {
429 bool pwm;
430 int i, ret;
431 struct xilinx_timer_priv *priv;
432 u32 one_timer, tcsr0;
433
434 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
435 if (!priv)
436 return ERR_PTR(-ENOMEM);
437
438 priv->regs = of_iomap(np, 0);
439 if (!priv->regs) {
440 ret = -ENXIO;
441 goto err_priv;
442 } else if (IS_ERR(priv->regs)) {
443 ret = PTR_ERR(priv->regs);
444 goto err_priv;
445 }
446
> 447 priv->read = ioread32;
> 448 priv->write = iowrite32;
449 /*
450 * We aren't using the interrupts yet, so use ENIT to detect endianness
451 */
452 tcsr0 = xilinx_timer_read(priv, TCSR0);
453 if (swab32(tcsr0) & TCSR_ENIT) {
454 ret = xilinx_timer_err(np, -EOPNOTSUPP,
455 "cannot determine endianness\n");
456 goto err_priv;
457 }
458
459 xilinx_timer_write(priv, tcsr0 | TCSR_ENIT, TCSR0);
460 if (!(xilinx_timer_read(priv, TCSR0) & TCSR_ENIT)) {
461 priv->read = xilinx_ioread32be;
462 priv->write = xilinx_iowrite32be;
463 }
464
465 /*
466 * For backwards compatibility, allow xlnx,one-timer-only = <bool>;
467 * However, the preferred way is to use the xlnx,single-timer flag.
468 */
469 one_timer = of_property_read_bool(np, "xlnx,single-timer");
470 if (!one_timer) {
471 ret = of_property_read_u32(np, "xlnx,one-timer-only", &one_timer);
472 if (ret) {
473 ret = xilinx_timer_err(np, ret, "xlnx,one-timer-only");
474 goto err_priv;
475 }
476 }
477
478 pwm = of_property_read_bool(np, "xlnx,pwm");
479 if (one_timer && pwm) {
480 ret = xilinx_timer_err(np, -EINVAL,
481 "pwm mode not possible with one timer\n");
482 goto err_priv;
483 }
484
485 priv->flags = FIELD_PREP(XILINX_TIMER_ONE, one_timer) |
486 FIELD_PREP(XILINX_TIMER_PWM, pwm);
487
488 for (i = 0; pwm && i < 2; i++) {
489 char int_fmt[] = "xlnx,gen%u-assert";
490 char bool_fmt[] = "xlnx,gen%u-active-low";
491 char buf[max(sizeof(int_fmt), sizeof(bool_fmt))];
492 u32 gen;
493
494 /*
495 * Allow xlnx,gen?-assert = <bool>; for backwards
496 * compatibility. However, the preferred way is to use the
497 * xlnx,gen?-active-low flag.
498 */
499 snprintf(buf, sizeof(buf), bool_fmt, i);
500 gen = !of_property_read_bool(np, buf);
501 if (gen) {
502 snprintf(buf, sizeof(buf), int_fmt, i);
503 ret = of_property_read_u32(np, buf, &gen);
504 if (ret && ret != -EINVAL) {
505 xilinx_timer_err(np, ret, "%s\n", buf);
506 goto err_priv;
507 }
508 }
509
510 if (!gen) {
511 ret = xilinx_timer_err(np, -EINVAL,
512 "generateout%u must be active high\n",
513 i);
514 goto err_priv;
515 }
516 }
517
518 ret = of_property_read_u32(np, "xlnx,count-width", &priv->width);
519 if (ret) {
520 xilinx_timer_err(np, ret, "xlnx,count-width\n");
521 goto err_priv;
522 } else if (priv->width < 8 || priv->width > 32) {
523 ret = xilinx_timer_err(np, -EINVAL, "invalid counter width\n");
524 goto err_priv;
525 }
526
527 priv->clk = xilinx_timer_clock_init(np, priv);
528 if (IS_ERR(priv->clk)) {
529 ret = xilinx_timer_err(np, PTR_ERR(priv->clk), "clock\n");
530 goto err_priv;
531 }
532
533 ret = clk_prepare_enable(priv->clk);
534 if (ret) {
535 xilinx_timer_err(np, ret, "clock enable failed\n");
536 goto err_clk;
537 }
538 clk_rate_exclusive_get(priv->clk);
539
540 if (pwm) {
541 ret = xilinx_pwm_init(dev, priv);
542 } else {
543 ret = xilinx_clocksource_init(priv);
544 if (!ret && !one_timer) {
545 ret = xilinx_clockevent_init(np, priv);
546 if (ret)
547 priv->flags |= XILINX_TIMER_ONE;
548 }
549 }
550
551 if (!ret)
552 return priv;
553
554 clk_rate_exclusive_put(priv->clk);
555 clk_disable_unprepare(priv->clk);
556 err_clk:
557 if (priv->flags & XILINX_TIMER_CLK)
558 clk_unregister_fixed_rate(priv->clk);
559 else
560 clk_put(priv->clk);
561 err_priv:
562 kfree(priv);
563 return ERR_PTR(ret);
564 }
565
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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