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Message-ID: <20210513110717.s2gr4l5upqzjkb5a@maple.lan>
Date:   Thu, 13 May 2021 12:07:17 +0100
From:   Daniel Thompson <daniel.thompson@...aro.org>
To:     Ard Biesheuvel <ardb@...nel.org>
Cc:     Arnd Bergmann <arnd@...nel.org>,
        Russell King <linux@...linux.org.uk>,
        Arnd Bergmann <arnd@...db.de>,
        "# 3.4.x" <stable@...r.kernel.org>,
        Marek Vasut <marek.vasut@...il.com>,
        Nathan Chancellor <nathan@...nel.org>,
        Nick Desaulniers <ndesaulniers@...gle.com>,
        Linus Walleij <linus.walleij@...aro.org>,
        Nicolas Pitre <nico@...xnic.net>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        Mike Rapoport <rppt@...nel.org>,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        clang-built-linux <clang-built-linux@...glegroups.com>
Subject: Re: [PATCH] ARM: fix gcc-10 thumb2-kernel regression

On Wed, May 12, 2021 at 02:38:36PM +0200, Ard Biesheuvel wrote:
> On Wed, 12 May 2021 at 10:13, Arnd Bergmann <arnd@...nel.org> wrote:
> >
> > From: Arnd Bergmann <arnd@...db.de>
> >
> > When building the kernel wtih gcc-10 or higher using the
> > CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y flag, the compiler picks a slightly
> > different set of registers for the inline assembly in cpu_init() that
> > subsequently results in a corrupt kernel stack as well as remaining in
> > FIQ mode. If a banked register is used for the last argument, the wrong
> > version of that register gets loaded into CPSR_c.  When building in Arm
> > mode, the arguments are passed as immediate values and the bug cannot
> > happen.
> >
> > This got introduced when Daniel reworked the FIQ handling and was
> > technically always broken, but happened to work with both clang and gcc
> > before gcc-10 as long as they picked one of the lower registers.
> > This is probably an indication that still very few people build the
> > kernel in Thumb2 mode.
> >
> > Marek pointed out the problem on IRC, Arnd narrowed it down to this
> > inline assembly and Russell pinpointed the exact bug.
> >
> > Change the constraints to force the final mode switch to use a non-banked
> > register for the argument to ensure that the correct constant gets loaded.
> > Another alternative would be to always use registers for the constant
> > arguments to avoid the #ifdef that has now become more complex.
> >
> > Cc: <stable@...r.kernel.org> # v3.18+
> > Cc: Daniel Thompson <daniel.thompson@...aro.org>
> > Reported-by: Marek Vasut <marek.vasut@...il.com>
> > Fixes: c0e7f7ee717e ("ARM: 8150/3: fiq: Replace default FIQ handler")
> > Signed-off-by: Arnd Bergmann <arnd@...db.de>
> 
> Nice bug!

Indeed. Many thanks for those involved with the find and fix!


Daniel.

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