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Message-ID: <20210513133834.GC1002214@nvidia.com>
Date: Thu, 13 May 2021 10:38:34 -0300
From: Jason Gunthorpe <jgg@...dia.com>
To: Jacob Pan <jacob.jun.pan@...ux.intel.com>
Cc: Christoph Hellwig <hch@...radead.org>,
LKML <linux-kernel@...r.kernel.org>,
iommu@...ts.linux-foundation.org, Joerg Roedel <joro@...tes.org>,
Lu Baolu <baolu.lu@...ux.intel.com>,
Jean-Philippe Brucker <jean-philippe@...aro.com>,
Yi Liu <yi.l.liu@...el.com>, Raj Ashok <ashok.raj@...el.com>,
"Tian, Kevin" <kevin.tian@...el.com>,
Dave Jiang <dave.jiang@...el.com>, wangzhou1@...ilicon.com,
zhangfei.gao@...aro.org, vkoul@...nel.org,
David Woodhouse <dwmw2@...radead.org>,
"Luck, Tony" <tony.luck@...el.com>
Subject: Re: [PATCH v4 1/2] iommu/sva: Tighten SVA bind API with explicit
flags
On Thu, May 13, 2021 at 06:00:12AM -0700, Jacob Pan wrote:
> > > If you want to do SVA PASID then it also must come with DMA APIs to
> > > manage the CPU cache coherence that are all NOP's on x86.
> >
> > Yes. And we have plenty of precende where an IOMMU is in "bypass" mode
> > to allow access to all memory and then uses the simple dma-direct case.
> I agree it is better not to expose the entire direct map. But the missing
> piece of using DMA APIs is the PASID. The caller needs the PASID value to
> do work submission once buffer is mapped.
You still haven't explained why the kernel driver should have a PASID at all.
Jason
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