linux-kernel - Re: [RESEND PATACH 1/1] iommu/vt-d: Use user privilege for RID2PASID translation

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <3e1f61dd-2f1e-0b11-934a-b0dab2e52d65@linux.intel.com>
Date:   Thu, 13 May 2021 11:06:10 +0800
From:   Lu Baolu <baolu.lu@...ux.intel.com>
To:     "Raj, Ashok" <ashok.raj@...el.com>
Cc:     baolu.lu@...ux.intel.com, Joerg Roedel <joro@...tes.org>,
        Will Deacon <will@...nel.org>, kevin.tian@...el.com,
        jacob.jun.pan@...el.com, yi.l.liu@...el.com,
        sanjay.k.kumar@...el.com, iommu@...ts.linux-foundation.org,
        linux-kernel@...r.kernel.org,
        Jacob Pan <jacob.jun.pan@...ux.intel.com>
Subject: Re: [RESEND PATACH 1/1] iommu/vt-d: Use user privilege for RID2PASID
 translation

Hi Ashok,

On 5/13/21 1:03 AM, Raj, Ashok wrote:
> On Wed, May 12, 2021 at 02:44:26PM +0800, Lu Baolu wrote:
>> When first-level page tables are used for IOVA translation, we use user
>> privilege by setting U/S bit in the page table entry. This is to make it
>> consistent with the second level translation, where the U/S enforcement
>> is not available. Clear the SRE (Supervisor Request Enable) field in the
>> pasid table entry of RID2PASID so that requests requesting the supervisor
>> privilege are blocked and treated as DMA remapping faults.
>>
>> Suggested-by: Jacob Pan <jacob.jun.pan@...ux.intel.com>
>> Fixes: b802d070a52a1 ("iommu/vt-d: Use iova over first level")
>> Signed-off-by: Lu Baolu <baolu.lu@...ux.intel.com>
>> ---
>>   drivers/iommu/intel/iommu.c | 7 +++++--
>>   drivers/iommu/intel/pasid.c | 3 ++-
>>   2 files changed, 7 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
>> index 708f430af1c4..f1742da42478 100644
>> --- a/drivers/iommu/intel/iommu.c
>> +++ b/drivers/iommu/intel/iommu.c
>> @@ -2525,9 +2525,9 @@ static int domain_setup_first_level(struct intel_iommu *iommu,
>>   				    struct device *dev,
>>   				    u32 pasid)
>>   {
>> -	int flags = PASID_FLAG_SUPERVISOR_MODE;
>>   	struct dma_pte *pgd = domain->pgd;
>>   	int agaw, level;
>> +	int flags = 0;
>>   
>>   	/*
>>   	 * Skip top levels of page tables for iommu which has
>> @@ -2543,7 +2543,10 @@ static int domain_setup_first_level(struct intel_iommu *iommu,
>>   	if (level != 4 && level != 5)
>>   		return -EINVAL;
>>   
>> -	flags |= (level == 5) ? PASID_FLAG_FL5LP : 0;
>> +	if (pasid != PASID_RID2PASID)
>> +		flags |= PASID_FLAG_SUPERVISOR_MODE;
>> +	if (level == 5)
>> +		flags |= PASID_FLAG_FL5LP;
> 
> Given that we are still not bought into the supervisor PASID, should we make this an
> explicit request before turning on SUPERVISOR mode always? Since
> pasid_set_sre() has no return, we have no way to fail it.
> 

The supervisor PASID is now supported in VT-d implementation. This patch
is only for RID2PASID. We need a separated patch to remove the superisor
pasid code once we reach a consensus.

Does this work for you?

Best regards,
baolu

> 
>>   
>>   	if (domain->domain.type == IOMMU_DOMAIN_UNMANAGED)
>>   		flags |= PASID_FLAG_PAGE_SNOOP;
>> diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
>> index 72646bafc52f..72dc84821dad 100644
>> --- a/drivers/iommu/intel/pasid.c
>> +++ b/drivers/iommu/intel/pasid.c
>> @@ -699,7 +699,8 @@ int intel_pasid_setup_second_level(struct intel_iommu *iommu,
>>   	 * Since it is a second level only translation setup, we should
>>   	 * set SRE bit as well (addresses are expected to be GPAs).
>>   	 */
>> -	pasid_set_sre(pte);
>> +	if (pasid != PASID_RID2PASID)
>> +		pasid_set_sre(pte);
>>   	pasid_set_present(pte);
>>   	pasid_flush_caches(iommu, pte, pasid, did);
>>   
>> -- 
>> 2.25.1
>>
>