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Message-ID: <58a35b85-eb0e-bc02-29be-0cae46bd75b8@kernel.org>
Date: Fri, 14 May 2021 14:43:45 -0700
From: Nathan Chancellor <nathan@...nel.org>
To: Arnd Bergmann <arnd@...nel.org>, Rob Clark <robdclark@...il.com>,
Sean Paul <sean@...rly.run>, David Airlie <airlied@...ux.ie>,
Daniel Vetter <daniel@...ll.ch>
Cc: Arnd Bergmann <arnd@...db.de>,
Nick Desaulniers <ndesaulniers@...gle.com>,
Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
Abhinav Kumar <abhinavk@...eaurora.org>,
Jonathan Marek <jonathan@...ek.ca>,
linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
clang-built-linux@...glegroups.com
Subject: Re: [PATCH] drm/msm/dsi: fix 32-bit clang warning
On 5/14/2021 2:30 PM, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@...db.de>
>
> clang is a little overzealous with warning about a constant conversion
> in an untaken branch of a ternary expression:
>
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c:975:48: error: implicit conversion from 'unsigned long long' to 'unsigned long' changes value from 5000000000 to 705032704 [-Werror,-Wconstant-conversion]
> .max_pll_rate = (5000000000ULL < ULONG_MAX) ? 5000000000UL : ULONG_MAX,
> ^~~~~~~~~~~~
>
> Rewrite this to use a preprocessor conditional instead to avoid the
> warning.
>
> Fixes: 076437c9e360 ("drm/msm/dsi: move min/max PLL rate to phy config")
> Signed-off-by: Arnd Bergmann <arnd@...db.de>
Reviewed-by: Nathan Chancellor <nathan@...nel.org>
> ---
> As found with another patch, using __builtin_choose_expr() would
> likely also work here, but doesn't seem any more readable.
> ---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> index e76ce40a12ab..accd6b4eb7c2 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> @@ -972,7 +972,11 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
> .restore_pll_state = dsi_7nm_pll_restore_state,
> },
> .min_pll_rate = 600000000UL,
> - .max_pll_rate = (5000000000ULL < ULONG_MAX) ? 5000000000ULL : ULONG_MAX,
> +#ifdef CONFIG_64BIT
> + .max_pll_rate = 5000000000UL,
> +#else
> + .max_pll_rate = ULONG_MAX,
> +#endif
> .io_start = { 0xae94400, 0xae96400 },
> .num_dsi_phy = 2,
> .quirks = DSI_PHY_7NM_QUIRK_V4_1,
>
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