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Message-ID: <20210514080708.2c108851@slackpad.fritz.box>
Date:   Fri, 14 May 2021 08:07:08 +0100
From:   Andre Przywara <andre.przywara@....com>
To:     Tobias Schramm <t.schramm@...jaro.org>
Cc:     Jernej Škrabec <jernej.skrabec@...il.com>,
        devicetree@...r.kernel.org, Rob Herring <robh+dt@...nel.org>,
        Maxime Ripard <mripard@...nel.org>,
        Chen-Yu Tsai <wens@...e.org>,
        linux-arm-kernel@...ts.infradead.org, linux-sunxi@...ts.linux.dev,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 1/7] ARM: dts: sun8i: v3s: add DMA controller to v3s
 dts

On Fri, 14 May 2021 01:30:18 +0200
Tobias Schramm <t.schramm@...jaro.org> wrote:

> The Allwinner V3s and V3 feature a DMA controller.
> This commit adds it to the V3s dtsi.
> 
> Signed-off-by: Tobias Schramm <t.schramm@...jaro.org>

Address, interrupt and clocks/reset match the manual.

Reviewed-by: Andre Przywara <andre.przywara@....com>

Cheers,
Andre

> ---
>  arch/arm/boot/dts/sun8i-v3s.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
> index eb4cb63fef13..f0296ab46137 100644
> --- a/arch/arm/boot/dts/sun8i-v3s.dtsi
> +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
> @@ -1,5 +1,6 @@
>  /*
>   * Copyright (C) 2016 Icenowy Zheng <icenowy@...c.xyz>
> + * Copyright (C) 2021 Tobias Schramm <t.schramm@...jaro.org>
>   *
>   * This file is dual-licensed: you can use it either under the terms
>   * of the GPL or the X11 license, at your option. Note that this dual
> @@ -172,6 +173,15 @@ nmi_intc: interrupt-controller@...00d0 {
>  			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
>  		};
>  
> +		dma: dma-controller@...2000 {
> +			compatible = "allwinner,sun8i-v3s-dma";
> +			reg = <0x01c02000 0x1000>;
> +			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_DMA>;
> +			resets = <&ccu RST_BUS_DMA>;
> +			#dma-cells = <1>;
> +		};
> +
>  		tcon0: lcd-controller@...c000 {
>  			compatible = "allwinner,sun8i-v3s-tcon";
>  			reg = <0x01c0c000 0x1000>;

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